- 专利标题: Clearance size reduction for backdrilled differential vias
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申请号: US15719168申请日: 2017-09-28
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公开(公告)号: US10470311B2公开(公告)日: 2019-11-05
- 发明人: Matthew Twarog , Hui He , Thomas W. Jetton
- 申请人: Juniper Networks, Inc.
- 申请人地址: US CA Sunnyvale
- 专利权人: Juniper Networks, Inc.
- 当前专利权人: Juniper Networks, Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Harrity & Harrity, LLP
- 主分类号: H05K1/11
- IPC分类号: H05K1/11 ; H05K1/02 ; H05K3/00 ; H05K3/46 ; H05K3/40
摘要:
A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.
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