- 专利标题: Reconfigurable Ethernet receiver and an analog front-end circuit thereof
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申请号: US16031988申请日: 2018-07-10
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公开(公告)号: US10361710B2公开(公告)日: 2019-07-23
- 发明人: Yu Lin , Marcello Ganzerli
- 申请人: NXP B.V.
- 申请人地址: NL Eindhoven
- 专利权人: NXP B.V.
- 当前专利权人: NXP B.V.
- 当前专利权人地址: NL Eindhoven
- 代理商 Rajeev Madnawat
- 优先权: EP17206786 20171212
- 主分类号: H03M1/12
- IPC分类号: H03M1/12 ; H03M1/00 ; H04B1/3805 ; H03M1/16 ; H04B1/401 ; H03M1/18
摘要:
The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.
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