Invention Grant
- Patent Title: 3DIC interconnect apparatus and method
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Application No.: US15944069Application Date: 2018-04-03
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Publication No.: US10361234B2Publication Date: 2019-07-23
- Inventor: Shih Pei Chou , Hung-Wen Hsu , Ching-Chung Su , Chun-Han Tsao , Chia-Chieh Lin , Shu-Ting Tsai , Jiech-Fun Lu , Shih-Chang Liu , Yeur-Luen Tu , Chia-Shiung Tsai
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/146
- IPC: H01L27/146 ; H01L23/48 ; H01L25/065 ; H01L21/768 ; H01L25/00 ; H01L21/683 ; H01L25/16

Abstract:
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
Public/Granted literature
- US20180226449A1 3DIC Interconnect Apparatus and Method Public/Granted day:2018-08-09
Information query
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