Vertical fin field effect transistor with integral U-shaped electrical gate connection
摘要:
A method of forming a complementary metal-oxide-semiconductor (CMOS) device is provided. The method includes forming a bottom spacer layer on a substrate around two adjacent vertical fins, and forming a first work function layer on both of the two adjacent vertical fins. The method further includes removing a portion of the first work function layer from one of the two adjacent vertical fins, and forming a second work function layer on the remaining portion of the first work function layer and on the one of the two adjacent vertical fins, wherein the second work function layer forms part of a gate structure on the one of the two adjacent vertical fins and an electrical connection to the first work function layer on the other of the two adjacent vertical fins.
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