Invention Grant
- Patent Title: Enhanced dynamic clock and voltage scaling (DCVS) scheme
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Application No.: US15094909Application Date: 2016-04-08
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Publication No.: US10296067B2Publication Date: 2019-05-21
- Inventor: Hee Jun Park , Cristian Duroiu
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP/Qualcomm
- Main IPC: G06F1/26
- IPC: G06F1/26 ; G06F1/324 ; G06F1/3234 ; G06F1/3287 ; G06F1/329 ; G06F1/3203

Abstract:
In certain aspects, a method for frequency scaling comprises determining whether only a subset of multiple processors is active, wherein the multiple processors share one or more resources. The method also comprises increasing a frequency of at least one processor in the subset of the multiple processors if a determination is made that only the subset of the multiple processors is active and the frequency of the at least one processor is below a frequency threshold. This may be done, for example, to increase the time duration of an idle mode for the one or more shared resources and achieve an overall power reduction for a system including the multiple processors, the one or more shared resources, and/or other function blocks.
Public/Granted literature
- US20170293340A1 ENHANCED DYNAMIC CLOCK AND VOLTAGE SCALING (DCVS) SCHEME Public/Granted day:2017-10-12
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