Invention Grant
- Patent Title: Transistor devices, memory cells, and arrays of memory cells
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Application No.: US13595832Application Date: 2012-08-27
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Publication No.: US10134916B2Publication Date: 2018-11-20
- Inventor: D. V. Nirmal Ramaswamy , Gurtej S. Sandhu
- Applicant: D. V. Nirmal Ramaswamy , Gurtej S. Sandhu
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/088 ; H01L29/788 ; H01L27/11521
Abstract:
A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate dielectric is between the first gate and the channel region. A second gate is proximate the channel region. A programmable material is between the second gate and the channel region. The programmable material includes at least one of a) a multivalent metal oxide portion and an oxygen-containing dielectric portion, or b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion. Memory cells and arrays of memory cells are disclosed.
Public/Granted literature
- US20140054709A1 Transistor Devices, Memory Cells, And Arrays Of Memory Cells Public/Granted day:2014-02-27
Information query
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