The invention relates to a shift register circuit, which possesses a plurality of series-connected stage shift register including a first transistor with the grid and the first resource/leakage connecting with output signal of the front stage register. The second transistor with the grid is connected with the second resource/leakage electrode of the first transistor; the first resource/leakage electrode is connected with a first clock signal and the output end of the second resource/leakage electrode. When the second transistor conducts and the first clock signal is high pressure level, the output end possesses a first voltage level. The low module is connected with the output end, the front stage and the second stage shift register output signal, the second voltage level and the third voltage level. When the front stage shift register output signal is a first voltage level, the output end is the third voltage level.