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发明授权
CN1612482B 延迟锁定回路及其时钟产生方法 失效 - 权利终止

延迟锁定回路及其时钟产生方法
摘要：
一种用于校正一时钟信号的占空的半导体存储器件，包括：第一时钟缓冲器，通过该第一时钟缓冲器的一非反相端接收一外部时钟信号以及通过该第一时钟缓冲器的一反相端接收一外部时钟限制信号，以输出第一时钟输入信号；第二时钟缓冲器，通过该第一时钟缓冲器的该非反相端接收该外部时钟限制信号以及通过该第一时钟缓冲器的该反相端接收该外部时钟信号，以输出第二时钟输入信号；以及延迟锁定回路，接收该第一时钟输入信号和该第二时钟输入信号，以产生占空校正时钟信号。
摘要（英）：

A semiconductor device for correcting a duty of a clock signal includes a first clock buffer for receiving an external clock signal through a non-inverting terminal of the first clock buffer and for receiving an external clock bar signal through an inverting terminal of the first clock buffer to thereby output a first clock input signal; a second clock buffer for receiving the external clock bar signal through the non-inverting terminal of the first clock buffer and for receiving the external clock signal through the inverting terminal of the first clock buffer to thereby output a second clock input signal; and a delay locked loop (DLL) for receiving the first clock input signal and the second clock input signal to thereby generate a duty corrected clock signal.

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