The invention provides a Fan-out process-based preparation method of a three-dimensional structure and belongs to the technical field of integrated circuit packaging. The method comprises the steps offirstly preparing a chip loading mark and vertical interconnection metals on a support plate wafer separately, preparing a groove in an area of the chip loading mark, filling the groove with an adhesive material and mounting a chip on the adhesive material; preparing an encapsulating layer on the support plate wafer and thinning the encapsulating layer by adopting a mechanical polishing process;preparing a rewiring layer and an under bump metallization layer; removing the support plate wafer and the adhesive material by adopting mechanical grinding and polishing processes until the back sideof the chip and the vertical interconnection metals are exposed outside; preparing a signal terminal on the exposed vertical interconnection metals by adopting a bumping process or an electroplatingprocess; and cutting a product subjected to the steps to obtain a single device unit and carrying out three-dimensional stacking and interconnection on the single device unit through a three-dimensional stacking process and an underfill process to obtain the three-dimensional structure.