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发明公开
CN107564877A 半导体元件封装体及半导体元件封装制程 无效 - 驳回

半导体元件封装体及半导体元件封装制程
摘要：
本发明涉及一种半导体元件封装体及半导体元件封装制程，包括下列步骤。首先，以三维列印方式在具有一凹槽的一载板上形成一图案化导电层以及覆盖图案化导电层的一防焊层，其中图案化导电层与防焊层自凹槽内延伸至凹槽外，而部分的图案化导电层被防焊层所暴露。接着，将至少一半导体元件设置于凹槽内的图案化导电层上，并使半导体元件与图案化导电层电性连接。本发明技术方案通过三维列印方式可在具有凹槽的载板上轻易地制作出图案化导电层及防焊层，可有效地降低三维封装的制程复杂度。可在载板的凹槽内形成连接线路，有助于降低半导体元件封装体的整体厚度。
摘要（英）：

The invention relates to a semiconductor element packaging body and semiconductor element packaging process; the process comprises the following steps: forming a patterning conducting layer and a solder mask covering the patterning conducting layer in a three dimensional line printing mode on a carrier plate with a groove, wherein the patterning conducting layer and the solder mask extend from thegroove to the outer side, and partial the patterning conducting layer is exposed by the solder mask; placing at least one semiconductor element on the patterning conducting layer in the groove, and electrically connecting the semiconductor element with the patterning conducting layer. The method uses the three dimensional line printing mode to easily make the patterning conducting layer and the solder mask on the carrier plate with the groove, thus effectively reducing three dimensional packaging process complexity; a connecting line is formed in the groove of the carrier plate, thus reducingthe semiconductor element packaging body integral thickness.

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