The invention relates to the semiconductor test technology, particularly to a test structure and a layout method therefor. The test structure is provided with a plurality of bonding pads, and a circuit under pad is arranged at the bottom of each bonding pad; the bonding pads comprise a first bonding pad, a second bonding pad, a third bonding pad and multiple fourth bonding pads; each circuit under pad is provided with multiple NMOS transistors which are the same in number and are in orientation distribution; the sources of all NMOS transistors are connected to the first bonding pad in parallel by adopting a first group of connecting lines; the substrates of all NMOS transistors are connected to the second bonding pad in parallel by adopting a second group of connecting lines; the gates of all NMOS transistors are connected to the third bonding pad in parallel by adopting a third group of connecting lines; the drains of the NMOS transistors in the same position are connected to one fourth bonding pad in parallel by adopting a fourth group of connecting lines, the NMOS transistors in different positions are corresponding to different fourth bonding pads; therefore, multiple test structures can be tested at the same time; and the current changing conditions of the drains of the NMOS transistors in different orientations in the circuit under pads can be analyzed, so that the offset direction in a position where a probe is clamped with a puncturing needle can be finally positioned.