The invention discloses a method and circuit using low voltage devices to realize ESD protection of a high voltage circuit; the method comprises the following steps: forming a charging current when a capacitor C0 receives an ESD pulse, forming voltage drop on a resistor R0, and controlling a second PMOS transistor MP1 and a third PMOS transistor to open; when the output voltage outputted by the second PMOS transistor MP1 and a first NMOS transistor MN0 is high level, and the bias voltage Vb2 outputted by the third PMOS transistor MP2 and the first PMOS transistor MP0 is high level, the third NMOS transistor MN2 and the second NMOS transistor MN1 are opened to release current. The method and circuit can improve the chip ESD protection ability, thus ensuring chip yield and reliability.