The invention discloses a NOR gate flash memory. The NOR gate flash memory comprises a substrate, oxidation layers, channel regions, tunneling oxidation layers, floating gate layers, control gate layers, interlayer dielectric substance layers, thin film layers, alloy layers, silicon nitride layers, source electrodes, drain electrodes, first metal layers, second metal layers and isolation layers. The substrate is provided with deep isolation channels in the first direction and is provided with shallow isolation channels in the second direction, and the depth of the deep isolation channels is larger than the depth of the shallow isolation channels. The oxidation layers are located in the deep isolation channels. The channel regions are located in the shallow isolation channels. The tunneling oxidation layers are located on the channel regions. The floating gate layers are located on the tunneling oxidation layers. The control gate layers are located on the floating gate layers. The interlayer dielectric substance layers are located between the floating gate layers and the control gate layers. The alloy layers and the silicon nitride layers are sequentially located on the control gate layers. The first metal layers are located on the source electrodes and the drain electrodes. The second metal layers are located on the first metal layers which are located on the drain electrodes. According to the NOR gate flash memory, floating gates are embedded into the substrate, the length of the isolation channels can be increased under the condition that the plane dimension is unchanged, the device operation needs are met, and thus the NOR gate flash memory can be scaled to be smaller than 45 nanometers.