In the present invention, a memory-cell power-source circuit (20) for each column comprises a first P-type MOS transistor (MP1) and a second P-type MOS transistor (MP2) connected in series between a first power source and a second power source, the contact point of the first P-type MOS transistor (MP1) and the second P-type MOS transistor (MP2) being output as the memory-cell power source. A control signal based on a column-selection signal and a write-control signal is input to the gate terminal of the first P-type MOS transistor (MP1), and a signal having an inverse level relative to the signal input to the gate terminal of the first P-type MOS transistor (MP1) is input to the gate terminal of the second P-type MOS transistor (MP2).