Disclosed is a shift register in a monolithic gate driver which does not cause abnormal operations, and which prevents increases in circuit surface area, current consumption and cost while shortening the clock fall and rise times. A shift register (410) operates on a four-phase clock signal, the phases of which are offset by 90 DEG , consisting of a two-phase clock signal (GCK1, GCK3) assigned to odd-numbered stages and a two-phase clock signal (GCK2, GCK4) assigned to even-numbered stages. In each stage of the shift register (410), when the potential of a first node is at the high level, the potential of the scan signal (GOUT) is the potential of a first clock (CKA). In such a structure, the potential of the first node contained in each stage is set to the high level on the basis of a scan signal pulse outputted from the previous stage, and is set to the low level on the basis of the scan signal pulse outputted from the third succeeding stage.