The invention discloses a failure positioning method for defects of a power metal-oxide-semiconductor chip, comprising steps of: 1) removing an aluminum layer on the surface of the power metal-oxide-semiconductor chip; and 2) as for the chip comprising a Ti/TiN diffusion impervious layer under the aluminum layer, perfusing current into grid, source and drain of the chip by directly inserting needles to perform EMMI (Emission Microscopy) or OBIRCH (Optical Beam Induced Resistance Change) analysis, and then positioning defects; and as for the chip comprising no diffusion impervious layer under the aluminum layer, depositing two metal pads by FIB (Focused Ion Beam) at an area free from transistors in the chip, further depositing a metal strip in connection with the metal pad at the edge of each metal pad by FIB, wherein the other ends of the two metal strips are respectively connected with the grid and the source, and completing EMMI or OBIRCH tests by using the two metal pads and the drain on the back of the chip, and then positioning the defects. The failure positioning method for the defects of the power metal-oxide-semiconductor chip has effect far better than liquid crystal analysis, and the defect positions can be rapidly and accurately found.