The invention relates to a high integration level system in a package (SIP) structure. The structure comprises a substrate, at least a group of wiring packaging layers on the substrate, a top inverted packaging layer on the wiring packaging layers and connection balls arranged below the substrate, wherein the wiring packaging layers comprise erected surface-mount layers, material sealing layers and wiring layers which are arranged on the substrate in sequence; the top inverted packaging layer comprises an inverted surface-mount layer, bottom padding material and a material sealing layer which are arranged on the wiring packaging layers in sequence; and electrical interconnection between the adjacent packaging layers or spaced packaging layers is realized via the wiring layers. Compared with the prior art, the structure which the invention requests to protect has the following beneficial effects: the final packaged products having the functions of the whole system instead of the functions of the single chip can be formed; the interference factors among the resistors, inductors and chips in the system are reduced; and besides, the more complex multilayer interconnection structure can be formed and higher integration level wafer SIP can be realized.