US09941906B2
An apparatus for polar coding includes an encoder circuit that implements a transformation c=u1N-sBN-s{tilde over (M)}n, where u1N-s, BN-s, {tilde over (M)}n, and C are defined over a Galois field GF(2k), k>1, N=2k, s
US09941904B2
The present invention provides a decoding method, a decoding apparatus, and a communications system, which implement multi-level coding in a manner combining soft-decision error correction coding and hard-decision error correction coding, implement multi-level decoding in a manner combining soft-decision error correction decoding and hard-decision error correction decoding, so as to integrate advantages of the two manners: compared with a manner in which soft-decision error correction coding and decoding are performed on multiple levels, a manner in which soft-decision error correction coding and decoding are performed on only one level reduces system complexity and resource overhead; and performing hard-decision error correction coding and decoding on other levels on a basis of performing soft-decision error correction coding and decoding on one level ensures gain performance, thereby meeting a gain requirement of a high-speed optical transmission system.
US09941891B2
A digital phase-locked loop includes a digital loop filter, a digitally controllable oscillator (DCO), and an injection-locked calibration-free time-to-digital converter (TDC) having a ring oscillator connected to the DCO via an input buffer that converts a sinusoidal DCO signal to a differential square wave signal provided to the ring oscillator such that ring oscillator frequency matches DCO frequency. A spur cancellation loop between the TDC and digital loop filter generates a spur cancellation signal based on an estimate of a spurious tone amplitude and phase. The spur cancellation signal is subtracted from TDC output signals prior to input to the digital loop filter. The spur cancellation loop may include a gradient descent strategy, or a feedforward strategy having a high-pass filter, integer delay chain, adaptive fractional delay, and signal averaging logic to cancel multiple internal and external spurs having frequencies that are not related to the reference clock frequency.
US09941885B2
Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.
US09941881B1
A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.
US09941876B2
Bootstrap diode circuits are disclosed. Example bootstrap diode circuits disclosed herein include a first diode having a first diode input coupled to a voltage supply and a first diode output. Disclosed bootstrap diode circuits additionally include a second diode having a second diode input coupled to the first diode output and a second diode output and a plurality of zener diodes coupled in series. The plurality of series-coupled zener diodes are further coupled in parallel with the second diode.
US09941875B2
A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.
US09941867B1
One embodiment relates to a pulse latch that includes a latch control logic circuit and a pulse latch circuit. The latch control logic circuit generates a plurality of control signals and selects a control signal of the plurality of control signals to output to the pulse latch circuit. Each control signal of the plurality of control signals causes the pulse latch circuit to operate in a different operating mode. Another embodiment relates to a method of generating control signaling for a pulse latch. A clock signal and a shifted clock signal are received. A plurality of inputs to a multiplexor are generated using the clock signal and the shifted clock signal. An input of the plurality of inputs is selected as an output of the multiplexor. The input is selected by the multiplexor using a plurality of multiplexor configuration bits.
US09941866B2
In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.
US09941851B2
An amplifier arrangement comprises N amplifier stages 101 to 10N, wherein N is an integer equal or greater than five. The amplifier arrangement comprises a cascade of quarter wavelength transmission line segments 111 to 11M coupled between an output of an amplifier of a first amplifier stage and an output node 15 of the amplifier arrangement. At least one intermediate junction 12 in the cascade of quarter wavelength transmission line segments comprises: a first amplifier coupled directly to the intermediate junction 12; and a second amplifier coupled to the same intermediate junction 12 via a connecting quarter wavelength trans mission line 131.
US09941848B1
In accordance with embodiments of the present disclosure, a transconductance with capacitances feedback compensation amplifier may include a capacitor in parallel with an inner feedback loop of the amplifier for providing cascade compensation to the amplifier.
US09941846B2
Techniques for providing multiple power supplies in electronic devices are disclosed. According to one aspect of the present invention, an appropriate power supply is provided only to accommodate a volume setting. In other words, there are at least two power supplies, one with a low voltage and the other with a high voltage. The high voltage power supply is only applied when there is a need to accommodate a volume setting. Thus the power consumption of the amplifiers is well controlled. As a result, the designs of the device and heat dissipation therein can be simplified and lowered in cost.
US09941840B2
A pulse generator is disclosed. The pulse generator can include a pulsed switch, such as a diode. The pulsed switched can be connected between an input source, such as an oscillator and a frequency multiplier.
US09941836B2
The present invention relates to a transient current and voltage protection device for electrical energy conversion systems connected to the power grid, comprising a diode bridge connected between the power grid and the power section of said inverter, upstream of the main filtering inductors.
US09941833B2
Provided is a converter for an HEV system. The converter includes a PCB, a PWM (IC) mounted on the PCB to output a plurality of PWM signals including a first PWM signal and a second PWM signal, a plurality of MOSFETs mounted on the PCB, the plurality of MOSFETs including a first MOSFET, which performs a switching operation according to the first PWM signal, and a second MOSFET which performs a switching operation according to the second PWM signal, and a plurality of inductors including a first inductor, which is magnetized according to the switching operation of the first MOSFET to operate in one phase, and a second inductor which is magnetized according to the switching operation of the second MOSFET to operate in other one phase.
US09941830B2
The current application is directed to various types of linear vibrational modules, including linear-resonant vibration modules that can be incorporated in a wide variety of appliances, devices, and systems to provide vibrational forces. The vibrational forces are produced by linear oscillation of a weight or member, in turn produced by rapidly alternating the polarity of one or more driving electromagnets. Feedback control is used to maintain the vibrational frequency of linear-resonant vibration module at or near the resonant frequency for the linear-resonant vibration module. Both linear vibration modules and linear-resonant vibration modules can be designed to produce vibrational amplitude/frequency combinations throughout a large region of amplitude/frequency space.
US09941828B2
The present disclosure is directed to a system and method for stabilizing sub-synchronous interaction (SSI) of a wind turbine generator connected to a power grid. More specifically, the method includes measuring an alternating-current (a-c) quantity of the power grid. Another step includes converting the a-c quantity to a d-q quantity and providing the d-q quantity to a d-q control loop within the controller. Another step includes altering, with a symmetric control component, a transfer function of the d-q control loop. The method also includes generating at least one d-q reference signal for the wind turbine generator based on the altered transfer function so as to achieve symmetric control of the generator. A further step includes generating a control signal for the generator based, at least in part, on the at least one d-q reference signal. The method also includes operating the generator based on the control signal.
US09941823B2
This disclosure discloses a motor control device configured to control a motor. The motor control device includes an inverter part, a gate driving circuit, a PWM generation circuit, at least one gate buffer, and a control part. The inverter part is configured to convert direct current into alternate current in response to a motor drive command. The gate driving circuit is configured to drive the inverter part. The PWM generation circuit is configured to generate a PWM signal applied to the gate driving circuit. The at least one gate buffer is disposed between the gate driving circuit and the PWM generation circuit. The control part is configured to apply a test signal to the gate buffer to determine abnormality of the gate buffer.
US09941822B2
Disclosed is an electromechanical generator for converting mechanical vibrational energy into electrical energy, the electromechanical generator comprising: a mass resiliently connected to a body by a biasing device and adapted to oscillate about an equilibrium point relative to the body with an oscillation amplitude, a transducer configured to convert oscillations of the mass about the equilibrium point relative to the body into electrical energy, and a resilient device disposed between the biasing device and one of the mass and the body, wherein the resilient device is configured to be deformed between the biasing device and the one of the mass and the body only when the oscillation amplitude exceeds a predetermined non-zero threshold amplitude. The resilient device may comprise one of a helical spring, an O-ring and a spring washer, such as a Belleville washer, a curved disc spring, a wave washer, and a split washer.
US09941817B2
High transfer sound pressure and high reception sensitivity are realized, and reliability is improved in terms of long term operation, in a capacitive detector-type ultrasonic transducer (CMUT). The ultrasonic transducer, which has a lower electrode (201), a hollow portion (202) that is formed on the lower electrode and surrounded by insulating films (209,208), an upper electrode (205) that is formed on the hollow portion, and a plurality of insulating film projections (204) that are formed in the hollow portion (202), comprises a plurality of rigid members (203) that are formed on the hollow portion, either the lower electrode (201) and/or the upper electrode (205) is disposed in a position that does not overlap with the insulating film projections (204) when viewed from the upper surface by carving out the portion that overlaps with the insulating film projections (204), and the respective rigid members (203) are disposed such that a region is present that overlaps with the insulating film projections (204) when viewed from the upper surface.
US09941816B2
A bidirectional current sensing circuit includes: a sensing resistor coupled between a load and a reference ground, a first and second auto-zero amplifiers coupled to the sensing resistor to sense the voltage across the sensing resistor, and an output transistor. One of the first and second auto-zero amplifiers operates in an output mode and the other of the first and second auto-zero amplifiers operates in a zeroing mode according to a polarity of a voltage across the sensing resistor. The output transistor has a first terminal providing a current sensing signal indicating a load current, a second terminal electrically connected to an inverting terminal of the one of the first and second auto-zero amplifiers operating in the output mode, and a control terminal electrically connected to an output terminal of the one of the first and second auto-zero amplifiers operating in the output mode.
US09941815B2
An object of the invention is to diagnose whether an overcurrent detecting function with respect to a power semiconductor element of a power conversion apparatus is normal. The power conversion apparatus of the invention is provided with IGBTs as the power semiconductor element which performs a switching operation to convert DC power supplied from a DC power source into AC power, an overcurrent detecting circuit, and an overcurrent simulating circuit. The IGBTs include an emitter sensing terminal which outputs a sense current according to a current flowing to an emitter electrode. The overcurrent detecting circuit detects the overcurrent flowing to the IGBTs on the basis of the sense current output from the emitter sensing terminal. The overcurrent simulating circuit outputs a simulation signal which simulates the overcurrent flowing to the IGBTs and toward the overcurrent detecting circuit.
US09941809B2
An inverter device includes an inverter device body portion and a protective cover that covers the inverter device body portion, and the protective cover integrally includes a front surface portion that covers the front surface of the inverter device body portion, a top surface portion that covers the top surface of the inverter device body portion, a first side surface portion that covers a first side surface of the inverter device body portion, and a second side surface portion that covers a second side surface of the inverter device body portion.
US09941798B2
In accordance with an embodiment, a method of operating a switched-mode power converter includes defining at least one of a minimum switching frequency threshold and a maximum switching frequency threshold; detecting valleys occurring in a voltage over the switching element when the switching element is in an off-state; and either in a quasi-resonant mode, switching the switching element on when an nth consecutive valley occurs, n being an integer equal to or greater than one, so that the actual switching frequency is at least one of: below the maximum switching frequency threshold and above the minimum switching frequency threshold, or in a forced switching frequency mode, switching the switching element on so that the actual switching frequency is the maximum or the minimum switching frequency.
US09941793B2
A voltage regulator includes circuitry for regulating a voltage output of the voltage regulator and a snubber circuit. The snubber circuit includes a switching device which is controlled to electronically connect or disconnect the snubber circuit with the circuitry of the voltage regulator device. The switching device may be controlled by a controller based on one or more parameters indicating a load of the voltage regulator device.
US09941792B2
Embodiments of a circuit for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter are disclosed. The circuit includes a ripple generation circuit coupled to a reference voltage input and to a sense voltage input, and having a reference voltage output to form a main loop. The circuit also includes a DC error correction circuit connected between the reference voltage input and the sense voltage input, and the reference voltage output of the ripple generation circuit. The DC error correction circuit includes a coarse DC error correction loop coupled between the sense voltage input and the reference voltage output and a fine DC error correction loop coupled between the reference voltage input and the reference voltage output. A method for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter, is also disclosed.
US09941788B2
A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.
US09941777B2
An electrical rotating machine comprises a stator including armature pole coils 14 capable of generating magnetic flux when energized, an inner rotor driven to rotate when the magnetic flux passes therethough, and an outer rotor driven to rotate in a magnetic path of the magnetic flux that passes through the first rotor, the outer rotor having portions of different materials, in permeability, which are situated along the periphery of the outer rotor, the inner rotor having a plurality of salient poles situated along the periphery of the inner rotor and wound by wound coils 34 which induce induced current when linked by the magnetic flux generated by the armature pole coils, the stator including a plurality of wound coils 51, 52, 53 winding around each of poles to constitute the armature pole coil for each of the plurality of salient poles.
US09941771B2
A number of variations may include a product comprising: a rotor core comprising a body, wherein the body includes an inner surface and an outer surface, a first end cap which extends radially from a first end of the body and a second end cap which extends radially from a second end of the body, wherein the first end cap, the second end cap, and the outer surface define an annular cavity; at least one sleeve adjacent at least one of the first end cap or the second end cap; at least one magnet contained within the annular cavity; and at least one bearing operatively attached to the at least one sleeve.
US09941752B2
Embodiments disclosed herein disclose a wireless charging system configured to generate and transmit power waves that, due to physical waveform characteristics, converge at a predetermined location in a transmission field to generate a pocket of energy. Receivers, associated with an electronic device being powered by the wireless charging system, may extract energy from these pocket of energy and then convert that energy into usable electric power for the electronic device associated with a receiver. The pocket of energy may manifest as a three-dimensional field (e.g., transmission field) where energy may be harvested by a receiver positioned within or nearby the pocket of energy. Video sensors capture actual video images of fields of view within the transmission field, and a processor identifies selected objects, selected events, and/or selected locations within the captured video images.
US09941751B2
A method for performing wireless charging control of an electronic device and an associated apparatus are provided, where the method includes: performing at least one detection operation at a direct current (DC) output terminal of a rectifier of the electronic device to generate at least one detection result, wherein two alternating current (AC) input terminals of the rectifier are coupled to two terminals of a power input coil of the electronic device, and the at least one detection operation is not performed at the power input coil; and estimating input power of the power input coil according to the at least one detection result with aid of a set of predetermined data, and sending a packet carrying information corresponding to the estimated input power, for performing wireless charging foreign object detection (FOD), wherein the set of predetermined data is stored in a non-volatile (NV) memory of the electronic device.
US09941747B2
A system for selecting a deselecting charging devices in a wireless power network is disclosed here. The system includes a graphical user interface from which a user may select or deselect devices to be charged in a wireless power network. The disclosed system may store records from different components of a wireless power network into a database distributed throughout said network with copies stored within the memory of wireless power transmitters.
US09941735B2
An uninterruptible power supply operates between a main supply input, a battery and a load, and comprises an input converter and an output converter. In a first mode of operation, AC mains power received at the supply input is converted by said input converter and output converter in series to provide an AC power supply to the load. In a second mode of operation, stored energy is released from the battery via the output converter to maintain the AC power supply to the load. A further converter can be used during the first mode of operation to charge the battery from a charging supply input. The charging current bypasses the input converter, allowing charging rate to be increased, without increasing a power rating of the input converter. The further converter may be bidirectional and be used also in the second mode.
US09941733B2
An electronic device includes a solar cell, a secondary battery that is charged by the solar cell, and a control circuit that switches between a charging period during which the charging of the secondary battery from the solar cell is performed and a communication period during which an optical signal is received by the solar cell. The optical signal includes a synchronization signal indicating the transmission of data and the data, and the communication period is configured to detect the synchronization signal. The control circuit extends the communication period to enable the solar cell to receive the whole data included in the optical signal.
US09941724B2
A method for controlling charging in an electronic device for managing the electronic device, to stably charge a battery is provided. The method includes setting alarm such that a wake up signal is generated after a time elapses when entry into a suspend mode is requested during charging a battery or in a charging stop state, entering the suspend mode, waking-up and determining a state of the battery wake up, and turning-on or -off the battery charging according to the determined state of the battery.
US09941722B2
A system (1-2) for efficiently transferring harvested vibration energy to a battery (6) includes a piezo harvester (2) generating an AC output voltage (VP(t)) and current (IPZ(t)) and an active rectifier (3) to produce a harvested DC voltage (Vhrv) and current (Ihrv) which charge a capacitance (C0). An enable circuit (17) causes a DC-DC converter (4) to be enabled, thereby discharging the capacitance into the converter, when a comparator (A0,A1) of the rectifier which controls switches (S1-S4) thereof detects a direction reversal of the AC output current (IPZ(t)). Another comparator (13) causes the enable circuit (17) to disable the converter (4) when the DC voltage exceeds a threshold (VREF), thereby causing the capacitance be recharged.
US09941720B2
In a lighting device, each of n circuit blocks includes a current controller, a storage element, a charging current controller, a charging rectifier element, and a discharging rectifier element. A first circuit block of the n circuit blocks is configured such that a pulsating voltage generated by rectifying a sine wave AC voltage is applied to the series circuit of the current controller and one light source electrically connected to the first circuit block. An i-th circuit block of the n circuit blocks is electrically connected in parallel to the current controller of an i-1-th circuit block via an i-1-th connection rectifier element.
US09941711B2
A method is provided for managing the level of charge of at least two batteries respectively powering a first and a second device. The devices are able to cooperate physically with one another via a modular interface, and the method includes a step of transferring energy from one of the batteries to the other of the batteries, the transferring step being implemented as a function of a level of charge of at least one of the batteries.
US09941707B1
The embodiments described herein include a transmitter that transmits a power transmission signal (e.g., radio frequency (RF) signal waves) to create a three-dimensional pocket of energy. At least one receiver can be connected to or integrated into electronic devices and receive power from the pocket of energy. The transmitter can locate the at least one receiver in a three-dimensional space using a communication medium (e.g., Bluetooth technology). The transmitter generates a waveform to create a pocket of energy around each of the at least one receiver. The transmitter uses an algorithm to direct, focus, and control the waveform in three dimensions. The receiver can convert the transmission signals (e.g., RF signals) into electricity for powering an electronic device. Accordingly, the embodiments for wireless power transmission can allow powering and charging a plurality of electrical devices without wires.
US09941696B2
Disclosed herein is a method and system for sharing power or energy across various power supply and control modules. More specifically, disclosed herein are systems and methods for distributing energy. As explained herein, the method discloses receiving, at a microgrid, data from a plurality of data sources. The data is then analyzed to forecast power needs associated with the microgrid. Using the data, the microgrid may determine whether and when to share power with the requesting module.
US09941694B2
A power supply system includes first and second DC power supplies and a power converter. The power converter includes first and third semiconductor elements electrically connected between respective nodes of a first node and a second node and a power line, second and fourth semiconductor elements electrically connected between respective nodes of the first node and the second node and a second power line, a fifth semiconductor element electrically connected between the first and second nodes, and first and second reactors. The first reactor is electrically connected in series with the first DC power supply, between the first node and the second power line. The second reactor is electrically connected in series with the second DC power supply, between the second power line and the second node. A control device controls on and off of the switching element included in the semiconductor element.
US09941693B2
In one embodiment, a bus coupled includes a voltage control circuit configured to selectively conduct a current from the first current source away from an output of the coupler to regulate a voltage drop across the another current source to a first value. An embodiment of a method of forming a bus coupler may include configuring a circuit to store energy from the input into a first storage element in response to receiving an active portion of an input signal, and to transfer energy from the storage element to the output after termination of the active portion of the input signal.
US09941687B2
Methods for operating a wind turbine system are provided. In one embodiment, a method includes adjusting a threshold direct current (DC) bus voltage for a dynamic brake in a wind turbine power converter above a reference DC bus voltage based on at least one system condition. The method further includes gating the dynamic brake on when an experienced DC bus voltage is equal to or greater than the threshold DC bus voltage, and inputting a dynamic brake condition into a controller when the dynamic brake is gated on. The method further includes determining if a grid fault has occurred, reducing power generation of the wind turbine if no grid fault has occurred, and blocking the power converter if a grid fault has occurred. The method further includes gating the dynamic brake off when the experienced DC bus voltage is less than the threshold DC bus voltage.
US09941679B1
An interlocking floor box assembly including one or more electrical boxes which may be securely ganged together to form a multi-gang floor box for mounting one or more electrical components, such as duplex outlets, directly in a concrete pour area or in a floor above a concrete base. Opposing side walls include an internal hub and an external hub respectively for interlocking two or more electrical boxes together. Other embodiments may include a tab and a corresponding slot on opposing walls on the electrical boxes to enable interlocking two or more boxes. The interlocking floor box assembly enables secure side to side interlocking of two or more boxes to form a multi-gang floor box. A cover plate and a lid assembly enable plug in of electrical cords into the duplex outlets with the plug ends of the cords recessed below the floor level.
US09941663B2
Vertical cavity light emitting sources that utilize patterned membranes as reflectors are provided. The vertical cavity light emitting sources have a stacked structure that includes an active region disposed between an upper reflector and a lower reflector. The active region, upper reflector and lower reflector can be fabricated from single or multi-layered thin films of solid states materials (“membranes”) that can be separately processed and then stacked to form a vertical cavity light emitting source.
US09941654B2
An apparatus for generating and amplifying laser beams at approximately 1 micrometer wavelength is disclosed. The apparatus includes an ytterbium-doped gain-crystal pumped by an ytterbium fiber-laser. The fiber-laser enables a pump wavelength to be selected that minimizes heating of the gain-crystal. The apparatus can be configured for generating and amplifying ultra-fast pulses, utilizing the gain-bandwidth of ytterbium-doped gain-crystals.
US09941648B2
A multi-outlet power strip comprises a channel assembly that includes a front channel having an integrated ground clamp configured to couple a ground wire of a received receptacle harness. In an example embodiment, the ground clamp is disposed at a first end of the channel assembly. A back channel can be mounted at a desired location. Supply wiring from a junction box or other type of power source can be provided to the back channel and coupled to receptacle wiring at a second opposing end of the front channel. The front channel can be coupled to the back channel. A back channel can be configured to engage an angle mount bracket in a manner that allows channel translation and passage of supply wiring. The angle mount bracket can independently support a back channel at an angled orientation while an installer secures the back channel to a mounting surface.
US09941643B2
Switchable grounded terminal loads are built into, or otherwise coupled to, connectors on motherboards and control devices. The terminal loads are coupled to the bus termination at the connector when the connector is “stuffed” (connected to a mating connector). The switchable grounded terminal loads replace dummy connectors in preventing empty “unstuffed” connectors from increasing error risks on active channels.
US09941638B2
An electrical cord having improved safety features comprises a plug having a body portion surrounding respective ends of first, second, and third electrical wires. A live receptacle is in electrical communication with the end of the first electrical wire. A neutral receptacle is in electrical communication with the end of the second electrical wire. A ground receptacle is in electrical communication with the end of the third electrical wire. The body portion surrounds and maintains the live, neutral, and ground receptacles in spaced apart orientation corresponding to blades on an electrical plug. An indicator is provided to indicate a state of the plug in which electricity is supplied to the plug in a proper polarity.
US09941637B2
A connection device in the present disclosure, which is a connection device capable of detachably connecting a cable, includes a first terminal to be connected to a second terminal of the cable, a holding mechanism for maintaining a connection state between the first terminal and the second terminal, and a controller that acquires environment information around the connection device and changes holding force of the holding mechanism based on the environment information.
US09941631B1
A plug attached to a terminal part of a cable includes a plug main body to be connected to an adaptor, a latch, which is provided at the plug main body so as to be elastically displaceable from an outside of the plug main body toward an outer surface of the plug main body and which is engaged to the adaptor, and a slider including a cover part that is disposed at the outside of the latch. When the cover part is pushed down toward the outer surface or when the slider is moved in an extraction direction in which the plug main body is to be extracted from the adaptor, the latch is pushed down toward the outer surface and the engaging state of the latch is released.
US09941627B2
This application relates to magnetically actuated electrical connectors. The electrical connectors includes movable magnetic elements that move in response to an externally applied magnetic field. In some embodiments, the electrical connectors includes recessed contacts that move from a recessed position to an engaged position in response to an externally applied magnetic field associated with an electronic device to which the connector is designed to be coupled. In some embodiments, the external magnetic field has a particular polarity pattern configured to draw contacts associated with a matching polarity pattern out of the recessed position.
US09941622B1
Various connectors are disclosed. The connectors include a sealing assembly for providing a seal around a cable extending through the connector. The sealing assembly can include a moveable shuttle, a sleeve, a stop component and a sealing boot. The sealing boot can be compressed between the sleeve and the shuttle as the shuttle moves towards the stop component. The sealing boot can be configured to change shape (e.g., buckle) around the cable in response to movement of the shuttle. The change in shape of the sealing boot can facilitate sealing around the cable. The connector can be configured to inhibit or prevent the sealing boot from being extruded of out of position in response to a pressure gradient between first and second ends of the connector.
US09941621B2
A card edge connector includes an insulative elongated housing and a plurality of contacts disposed in the housing. The housing includes a pair of side walls extending along a longitudinal direction with a central slot therebetween in a transverse direction perpendicular to the longitudinal direction. Each side wall includes a plurality of passageways to receive the corresponding contacts, respectively. Each contact has the retaining section, a contacting section extending from one side of the retaining section, and a tail section extending from the other side of the retaining section. Each contact at a lower position is associated with a corresponding wiping terminal at an upper position in the same passageway.
US09941614B2
A socket connector includes a housing mounted on a substrate, a plurality of socket terminals that is held by the housing. The plurality of socket terminals is, on one end side thereof, conductively connected to a single connection pad provided in a circuit pattern of the substrate, and is, on the other end side thereof, conductively connected to a plug terminal that is to be a connection mate. Each of the socket terminals includes a substrate connection portion that is fixed to a connection pad, a contact portion that comes into conductive contact with the substrate, and a connection piece portion that connects the contact portion and the substrate connection portion to each other. The connection piece portion including a plurality of branched pieces forming conductive paths that connect, in a parallel manner, the contact portion and the substrate connection portion splits an electric current in a parallel manner.
US09941613B2
An electrical connector is disclosed. The electrical connector has an insulating housing extending in a longitudinal direction and having a first insertion slot and a second insertion slot parallel to the first insertion slot, a plurality of first terminals disposed separately on an upper portion of the first insertion slot along the longitudinal direction, a plurality of second terminals disposed on the upper portion of the first insertion slot and spaced apart from the plurality of first terminals, a plurality of third terminals disposed separately on a lower portion of the first insertion slot along the longitudinal direction, a plurality of fourth terminals disposed separately on an upper portion of the second insertion slot along the longitudinal direction, and a balance structure disposed on an end of the insulating housing in the longitudinal direction.
US09941608B2
A plug connector arrangement having a plug connector and a cable connected thereto, at least one inner conductor and an outer conductor surrounding the inner conductor, wherein the outer conductor of the cable is electrically connected to an outer conductor housing of the plug connector. The plug connector arrangement additionally has a sleeve part which surrounds the inner conductor, has approximately the same inner diameter (D) as the outer conductor (34) of the cable, adjoins a front axial end (A) of the outer conductor, and continues a shielding of the inner conductor in the direction of the front cable end.
US09941592B2
Unit cell including a receive antenna, a transmit antenna, and including first and second radiation surfaces separated from each other by a separation area, a phase-shift circuit comprising switches, each having an on, respectively off, state, wherein the corresponding switch allows, respectively blocks, the flowing of a current between the first and second radiation surfaces; a ground plane; a first printed circuit board including a first surface provided with the receive antenna, and a second opposite surface provided with the ground plane; a wafer of a semiconductor material including a first surface provide with first and second radiation surfaces and wherein the switches are formed in the separation area, monolithically with the transmit antenna.
US09941590B2
Various embodiments of a single structure multiple mode antenna are described. The antenna is preferably constructed having a first inductor coil that is electrically connected in series with a second inductor coil. The antenna is constructed having a plurality of electrical connections positioned along the first and second inductor coils. A plurality of terminals facilitates connection of the electrical connections thereby providing numerous electrical connection configurations and enables the antenna to be selectively tuned to various frequencies and frequency bands. In addition, the antenna comprises a variety of magnetic shielding materials that are positioned through the antenna structure. These magnetic materials are designed to help shape the magnetic fields being emitted by the respective inductor coils.
US09941581B2
A housing for an electronic device, including an aluminum layer enclosing a volume that includes a radio-frequency (RF) antenna is provided. The housing includes a window aligned with the RF antenna; the window including a non-conductive material filling a cavity in the aluminum layer; and a thin aluminum oxide layer adjacent to the aluminum layer and to the non-conductive material; wherein the non-conductive material and the thin aluminum oxide layer form an RF-transparent path through the window. A housing for an electronic device including an integrated RF-antenna is also provided. A method of manufacturing a housing for an electronic device as described above is provided.
US09941576B2
An antenna device includes a power supply coil to which a near field communication circuit is connected, a near field communication coil that is coupled to an antenna coil of a communication target and the power supply coil via a magnetic field and that resonates at the frequency of a near field communication signal, and a non-contact charging coil that is connected to a non-contact charging control circuit and that is coupled to a target coil for non-contact charging. The power supply coil and the non-contact charging coil are provided on the same plane or on planes that are close to each other. The non-contact charging coil is superposed with the near field communication coil when viewed in plan view, and the shortest distance between the power supply coil and the NFC coil is smaller than the shortest distance between the power supply coil and the non-contact charging coil.
US09941573B2
A problem with conventional article management systems has been that the management scheme for articles. The present invention addresses this problem by providing an article management system comprising: a transmitting antenna for transmitting a radio signal; a receiving antenna for receiving a radio signal; a article to be managed positioning region whereat articles to be managed are placed; an RF tag provided with a tag transmitting unit which electromagnetically couples with the transmitting antenna and the receiving antenna; and an RFID reader which sends a transmission signal to the RF tag via the transmitting antenna and receives a response signal outputted by the tag transmitting unit via the receiving antenna. The RFID reader detects whether or not a article to be managed is present by detecting for changes in the operation characteristics of the tag transmitting unit due to the article to be managed according to changes in either the strength or phase of the response signal from the RF tag.
US09941566B2
Disclosed are various embodiments for transmitting energy conveyed in the form of a guided surface-waveguide mode along the surface of a lossy medium such as, e.g., a terrestrial medium by exciting a guided surface waveguide probe.
US09941560B2
A broadband fully micromachined transition from rectangular waveguide to cavity-backed coplanar waveguide line for submillimeter-wave and terahertz application is presented. The cavity-backed coplanar waveguide line is a planar transmission line that is designed and optimized for minimum loss while providing 50 Ohm characteristic impedance. This line is shown to provide less than 0.12 dB/mm loss over the entire J-band. The transition from cavity-backed coplanar waveguide to a reduced-height waveguide is realized in three steps to achieve a broadband response with a topology amenable to silicon micromachining. A novel waveguide probe measurement setup is also introduced and utilized to evaluate the performance of the transitions.
US09941559B2
A metal-air battery comprising an emulsified or dispersed aqueous/ionic liquid two phase electrolyte system is provided. The two phase electrolyte system contains an aqueous phase and an ionic liquid phase wherein an amount of water exceeds the aqueous solubility of the ionic liquid. In one embodiment the metal-air battery is a lithium-air battery.
US09941545B2
Disclosed is an electrolyte solution for lithium secondary batteries, including a cyclic sulfonic acid ester represented by the general formula (1): wherein, in the general formula (1), R1 and R2 each independently represent a hydrogen atom, an alkyl group having 1 to 5 carbon atoms, halogen or an amino group with the proviso that R1 and R2 do not represent hydrogen atoms at the same time; and R3 represents methylene which may be substituted with fluorine. Batteries using this electrolyte solution are excellent in battery properties and storage characteristics.
US09941541B2
In a fuel cell stack, voltage detecting terminals are disposed on a second separator and a third separator of a power generation unit, whereas a voltage detecting terminal is not disposed on a first separator of the power generation unit. Among terminal plates of the fuel cell stack, another voltage detecting terminal is disposed only on the terminal plate that is in contact with the first separator.
US09941537B2
Problem: To provide a fuel cell module and a fuel cell device with improved power output.Resolution means: A fuel cell module (27) according to the present invention includes: a housing (2); a plurality of cell stack devices (1) arranged inside the housing (2), each cell stack device (1) including a cell stack (3) in which a plurality of fuel cells (2) that generate power using fuel gas and oxygen-containing gas are arranged; and exhaust gas discharge paths (39, 40) formed between the cell stack devices (1) for discharging the exhaust gas from the fuel cells. Consequently, the exhaust gases can be efficiently discharged, thereby improving the power output. A fuel cell device (52) can have improved power output by being provided with the above-described fuel cell module (27).
US09941532B2
An objection is to provide a technology by which a decline in the starting performance of a fuel cell system may be controlled in a low-temperature environment. A control method of a fuel cell system includes a temperature acquisition step of acquiring a temperature of the fuel cell at start-up of the fuel cell; and an exhaust gas control step of restricting, when the temperature of the fuel cell is below a predetermined value, a flow rate of an exhaust gas flowing into a flow path configuring portion that configures at least a part of a flow path of the exhaust gas of the fuel cell as compared to the flow rate of the exhaust gas flowing into the flow path configuring portion when the temperature of the fuel cell is equal to or less than the predetermined value.
US09941521B2
The disclosure is to provide a method for producing a core-shell catalyst that is able to increase the power generation performance of a membrane electrode assembly. A dispersion is prepared, in which a palladium-containing particle support, in which palladium-containing particles are supported on an electroconductive support, is dispersed in water; hydrogen gas is bubbled into the dispersion; the palladium-containing particles are acid treated after the bubbling; copper is deposited on the surface of the palladium-containing particles by applying a potential that is nobler than the oxidation reduction potential of copper to the palladium-containing particles in a copper ion-containing electrolyte after the acid treatment; and then a shell is formed by substituting the copper deposited on the surface of the palladium-containing particles with platinum by bringing the copper deposited on the surface of the palladium-containing particles into contact with a platinum ion-containing solution.
US09941506B2
Part of an electrode, specifically a current collector and an active material layer, for a secondary battery is subjected to cutting processing to have a complex shape. For example, a stack of the first current collector and the first active material layer has a first slit and a second slit. The first slit extends from a first edge of the stack. The second slit extends from a second edge of the stack, is the slit closest to an electrode tab, and is not parallel or vertical to the longest edge of the current collector.
US09941505B2
A battery includes a shell, a core and a protection component received in the shell. The core includes a first electrode tab connected to a first current collector and a second electrode tab connected to a second current collector of the core. The protection component includes two insulating layers and a conducting layer disposed between two insulating layers. The conducting layer defines a first end electrically connected to the first electrode tab and a second end configured as a free end, and an outmost current collector of the core is configured by the second current collector.
US09941504B2
The present invention is an all-solid-state electrode body including: a positive electrode via that is formed in a negative electrode connection layer, and connects a plurality of a positive electrode connection layers adjacent to each other in a first direction; a negative electrode via that is formed in the positive electrode connection layer, and connects a plurality of the negative electrode connection layers adjacent to each other in the first direction; a positive electrode current collector layer which is exposed on a first surface that faces one side of the first direction in a stacked body, and is connected to the positive electrode connection layer via the positive electrode via; and a negative electrode current collector layer which is exposed on the first surface in the stacked body, and is connected to the negative electrode connection layer via the negative electrode via.
US09941503B2
A rechargeable battery according to one or more exemplary embodiments includes: a pair of electrode assemblies, each including a first electrode including a coated region, a tab, and a connecting tab, a second electrode including a coated region, a tab, and a connecting tab, and a separator between the first electrode and the second electrode, the first electrode, the separator, and the second electrode being wound; a case accommodating the pair of electrode assemblies; a cap plate at an opening of the case and defining terminal openings; and first and second electrode terminals respectively connected to the tabs of the first and second electrodes and respectively passing through the terminal openings. The pair of electrode assemblies are electrically connected to each other via the connecting tabs.
US09941502B2
A signal collection and power connection assembly of a power battery module, a power battery module and a vehicle are provided. The assembly includes a substrate, a power connection member fixed on the substrate, a power connection line formed by a first sheet-like conductor disposed on the substrate, a signal collection line formed by a second sheet-like conductor disposed on the substrate, and a signal collection member disposed on the substrate and coupled with the signal collection line. A terminal of the power connection line is coupled with the power connection member, and a terminal of the signal collection line is coupled with the power connection member.
US09941497B2
Provided are a secondary battery separator having good heat durability, high adhesion property with the electrode active material layer formed on the current collector, and good anti-blocking property, and a secondary battery having such a secondary battery separator. The secondary battery separator of the present invention includes an organic separator layer, a heat-durable layer formed adjacent to at least one surface of the organic separator layer, and an adhesive layer formed on the heat-durable layer, wherein the heat-durable layer contains non-conductive particles and a binder, and the adhesive layer contains a particulate polymer having a glass transition temperature (Tg) of 10 to 100° C.
US09941494B2
A battery pack including a battery cell, a plurality of electrode tabs coupled to and extending from terminals of the battery cell, a protect circuit module (PCM) to control charging and discharging of the battery cell, a flexible printed circuit board (FPCB) including a plurality of connection pads coupled to the electrode tabs and electrically coupling the battery cell to the PCM, and a case accommodating the battery cell, the electrode tabs, the PCM, and the FPCB, wherein the case includes a first case accommodating the battery cell and a second case covering the first case, and wherein the first case includes ribs extending toward the second case and has cut-out grooves at regions corresponding to the connection pads.
US09941493B2
A power storage device packaging material includes: a base material layer; a metal foil layer formed on one surface of the base material layer via an adhesive layer; and a sealant layer arranged on a surface of the metal foil layer, the surface of the metal foil layer being on the opposite side to the base material layer, wherein the base material layer contains a polyester resin that contains a polyester elastomer and/or an amorphous polyester.
US09941492B2
A flexible secondary battery includes an electrode assembly and external material surrounding the electrode assembly having at least one bonding portion, wherein the external material is bonded to itself at the at least one bonding portion, and the at least one bonding portion extends in a lengthwise direction of the electrode assembly at an edge of the electrode assembly.
US09941489B2
An organic light emitting diode display device includes a first driving voltage line including a first portion extending in a first direction and a second portion having a larger width than the first portion in a second direction perpendicular to the first direction. The second portion overlaps a gate electrode of a driving thin film transistor, an interlayer insulating layer is between the second portion and the gate electrode of the driving thin film transistor.
US09941480B2
A method for processing a perovskite photoactive layer. The method comprises depositing a lead salt precursor onto a substrate to form a lead salt thin film, depositing a second salt precursor onto the lead salt thin film, annealing the substrate to form a perovskite material.
US09941477B2
A compound for an organic photoelectric device is represented by Chemical Formula 1, and an organic photoelectric device, an image sensor and an electronic device include the same.
US09941475B2
Provided is a method for manufacturing a highly reliable display device. The method includes steps of providing a first layer, a first insulating layer, an electrode, and a second insulating layer over a first surface of a first substrate; removing a part of the second insulating layer to provide a first opening; providing a display element and a second layer over the second insulating layer; providing a third layer and a third insulating layer over a second surface of a second substrate; removing part of the third layer and part of the third insulating layer to provide a second opening; overlapping the first substrate and the second substrate with a bonding layer positioned therebetween such that the first surface and the second surface face each other and the first opening and the second opening have an overlap region; separating the first substrate and the first layer from the first insulating layer; providing a third substrate such that the first insulating layer and the third substrate overlap with each other; separating the second substrate, part of the bonding layer, part of the second layer, and the third layer from the third insulating layer; and providing a fourth substrate such that the third insulating layer and the fourth substrate overlap with each other.
US09941473B2
Various embodiments relate to a method for closely connecting an organic optoelectronic component to a connection piece, including forming a first cavity in the organic optoelectronic component, wherein the first cavity has at least a first opening, introducing a connecting structure through the first opening into the first cavity, wherein the connecting structure has a first fixing area, wherein the first fixing area is configured partially complementarily to the form of the first cavity, forming a second cavity in a connection piece, wherein the second cavity has at least a second opening, wherein the second cavity is configured partially complementarily to the form of the second fixing area, and introducing a second fixing area through the second opening into the second cavity, and forming a friction-fitting connection of the organic optoelectronic component with the connecting piece once the connecting structure has been introduced into the first and the second cavity.
US09941471B2
A method for manufacturing a PCRAM memory includes forming in a first dielectric layer arranged on a substrate, which includes bottom electrodes, a first rectilinear trench opening onto the set of electrodes; depositing a first active layer in the first trench, such that the first active layer is in electrical contact with the electrodes; covering the first active layer with a second dielectric layer; etching, in the second and second dielectric layers and the first active layer, additional rectilinear trenches oriented perpendicularly to the first trench, to obtain a group of memory devices each including a portion of the first active layer in electrical contact with one of the electrodes; filling the additional trenches with a sacrificial dielectric material; performing an anisotropic etching of the sacrificial material to expose a side surface of each portion of the first active layer; and covering the side surface with a second active layer.
US09941466B2
A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel insulator material comprises MgO and the magnetic electrode material comprises Co and Fe. B is proximate opposing facing surfaces of the tunnel insulator material and the magnetic electrode material. B-absorbing material is formed over a sidewall of at least one of the magnetic electrode material and the tunnel insulator material. B is absorbed from proximate the opposing facing surfaces laterally into the B-absorbing material. Other embodiments are disclosed, including magnetic tunnel junctions independent of method of manufacture.
US09941463B2
Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.
US09941456B2
Disclosed is a thermoelectric material with excellent thermoelectric conversion performance. The thermoelectric material includes a matrix having Cu and Se, a Cu-containing particle, and an Ag-containing structure.
US09941453B2
A light emitting device includes a light emitting element having a first face positioned on an emission face side of the light emitting device, a second face opposing the first face, and lateral faces disposed between the first face and the second face, a light transmissive member formed from a resin-containing material, covering at least a portion of the lateral faces of the light emitting element and having a first face positioned on the emission face side, a covering member covering an exterior of the light transmissive member and having a first face positioned on the emission face side, a wavelength converting member covering the first face of the light emitting element, the first face of the light transmissive member, and the first face of the covering member, and a light reflective film including a first reflective film portion made of an inorganic material disposed between the exterior of the light transmissive member and the covering member, and a second reflective film portion made of an inorganic material disposed between the first face of the covering member and the wavelength converting member.
US09941452B2
A display device is provided. The display device includes a first substrate, a display unit, a second substrate, and a light shielding structure. The display unit is disposed on the first substrate and includes at least one light emitting diode chip. The light shielding structure surrounds the light emitting diode chip of the display units and is located between the first substrate and the second substrate.
US09941451B2
A light emitting device includes a wiring board, a light emitting element, and a protection film. The wiring board includes a base member, and positive and negative wiring layer parts. The positive and negative wiring layer parts are arranged on or above the upper surface of the base member. The light emitting element is mounted on the wiring layer parts in a flip-chip manner. The protection film covers the base member, the wiring layer parts and the light emitting element, and is formed of an inorganic material for serving as the exterior surface of the light emitting device. Each of the wiring layer parts has a curved outer-side edge. The curvature of the outer-side edge is substantially constant.
US09941450B2
A bottom electrically conductive surface is disposed on the top surface of a substrate and a top electrically conductive surface disposed on the bottom surface of a superstrate. A bare die electronic device is disposed with at least one of its top conductor in direct electrical communication with the bottom electrically conductive surface and/or its bottom conductor in direct electrical communication with the top conductive surface. A non-conductive adhesive secures the substrate to the superstrate so that the bare die electronic device is retained in direct electrical communication. The non-conductive adhesive has a melting point temperature at least greater than a minimum operating temperature of the operating temperature range of the bare die, so that the non-conductive adhesive does not melt and flow thereby preventing a separation or degradation of the direct electrical connection of the bare die electronic device.
US09941445B2
The invention relates to a method for texturing a semiconductor substrate (1), comprising steps consisting in forming a plurality of cavities of random shapes, depths and distribution, in an etch mask (2), by means of non-homogeneous reactive-ion etching, forming a first rough random design, and etching the substrate using the etch mask, by means of reactive-ion etching, in such a way as to transfer the first rough random design into the substrate and to produce a second rough random design (200), comprising cavities (20) of random shapes, depths (d2r) and distribution, on the surface of the substrate.
US09941439B2
A thyristor includes a first conductivity type semiconductor layer, a first conductivity type carrier injection layer on the semiconductor layer, a second conductivity type drift layer on the carrier injection layer, a first conductivity type base layer on the drift layer, and a second conductivity type anode region on the base layer. The thickness and doping concentration of the carrier injection layer are selected to reduce minority carrier injection by the carrier injection layer in response to an increase in operating temperature of the thyristor. A cross-over current density at which the thyristor shifts from a negative temperature coefficient of forward voltage to a positive temperature coefficient of forward voltage is thereby reduced.
US09941435B2
A photovoltaic module is disclosed. The photovoltaic module has a first side directed toward the sun during normal operation and a second, lower side. The photovoltaic module comprises a perimeter frame and a photovoltaic laminate at least partially enclosed by and supported by the perimeter frame. The photovoltaic laminate comprises a transparent cover layer positioned toward the first side of the photovoltaic module, an upper encapsulant layer beneath and adhering to the cover layer, a plurality of photovoltaic solar cells beneath the upper encapsulant layer, the photovoltaic solar cells electrically interconnected, a lower encapsulant layer beneath the plurality of photovoltaic solar cells, the upper and lower encapsulant layers enclosing the plurality of photovoltaic solar cells, and a homogenous rear environmental protection layer, the rear environmental protection layer adhering to the lower encapsulant layer, the rear environmental protection layer exposed to the ambient environment on the second side of the photovoltaic module.
US09941430B2
A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers.
US09941426B2
Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask. The mask includes a pattern defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate. The patterning the substrate includes anisotropically removing portions of the substrate exposed by the plurality of spaces.
US09941423B2
A method for manufacturing a thin film solar cell includes: depositing a transparent first rear electrode on a first surface of a transparent substrate; depositing a second rear electrode having a high-conductive metal on the first rear electrode; performing a first laser scribing process to separate a double layer of the first and second rear electrodes; depositing a light absorption layer having selenium (Se) or sulfur (S) on the second rear electrode; performing a second laser scribing process by inputting a laser to a second surface of the transparent substrate to separate the light absorption layer; depositing a transparent electrode on the light absorption layer; and performing a third laser scribing process by inputting a laser to the second surface to separate the transparent electrode. Accordingly, patterning may be performed in a substrate-incident laser manner to improve price, productivity and precision of the patterning process.
US09941422B2
Provided are a transparent conductive film having a simple manufacturing process and high transparency, high photoelectric conversion efficiency, and excellent durability and an organic photoelectric conversion element using this transparent conductive film.The transparent conductive film of the present invention is formed by laminating a ground layer which contains a nitrogen-containing organic compound and a metal thin film layer which contains a metal element of Group 11 of the periodic table and has a thickness of from 2 to 10 nm. In addition, the organic photoelectric conversion element of the present invention has a first electrode, a second electrode, and a photoelectric conversion layer present between the first electrode and the second electrode, and at least one of the first electrode and the second electrode of the organic photoelectric conversion element is a transparent conductive film formed by laminating the ground layer which contains the nitrogen-containing organic compound and the metal thin film layer which contains a metal element of Group 11 of the periodic table and has a thickness of from 2 to 10 nm.
US09941413B2
It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.
US09941409B2
A thin film transistor substrate includes a semiconductor channel layer made of an oxide semiconductor, protective insulating layers that cover the semiconductor channel layer, a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode. The second source electrode is located on the first source electrode and connected with the semiconductor channel layer through a first contact hole. The second drain electrode is located on the first drain electrode and connected with the semiconductor channel layer through a second contact hole.
US09941404B2
A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.
US09941402B2
A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure includes a first doping region at a front side surface of the substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the substrate to at least a part of the front side surface in contact with the wiring structure. An edge termination doping region laterally surrounds the first and second active areas. The edge termination doping region and the first doping region have a first conductivity type, and the common doping region has a second conductivity type. A resistive connection between the edge termination doping region and the first doping region is present at least during reverse operating conditions of the semiconductor device.
US09941401B2
A semiconductor device includes a semiconductor stacked structure in which a semiconductor layer including an electron supply layer and an electron transit layer is stacked, and a gate electrode contacting with the semiconductor layer included in the semiconductor stacked structure or an insulating layer. The portion of the gate electrode contacting with the semiconductor layer or the insulating layer is an oxide of a metal configuring the portion of the gate electrode contacting with the semiconductor layer or the insulating layer.
US09941399B2
A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.
US09941397B2
In a trench deeper than a thickness of a p-type base layer and configured by a first trench and a second trench, a second trench positioned at a lower portion is configured by a third trench and a fourth trench. A width of the second trench along an X direction is expanded more than the first trench positioned above the second trench. Along the X direction, the extent to which the second trench is expanded differs for the third trench and the fourth trench. Thus, a width of the lower portion of the trench differs along a Y direction, enabling reduced gate capacitance compared to uniform expansion along a transverse direction of the trench. Further, ON voltage may be reduced and switching capability may be improved.
US09941393B2
A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.
US09941384B2
A semiconductor device includes a first III-V compound layer on a substrate, a second III-V compound layer on the first III-V compound layer, in which a material of the first III-V compound layer is different from that of the second III-V compound layer, a gate metal stack disposed on the second III-V compound layer, a source contact and a drain contact disposed at opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer.
US09941382B2
In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer.
US09941370B2
Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.
US09941368B2
Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.
US09941367B2
A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
US09941357B2
A power MOSFET includes a substrate, a semiconductor layer, a first gate, a second gate, a thermal oxide layer, a first CVD oxide layer, and a gate oxide layer. The semiconductor layer is formed on the substrate and has at least one trench. The first gate is located inside the trench. The second gate is located inside the trench on the first gate, wherein the second gate has a first portion and a second portion, and the second portion is located between the semiconductor layer and the first portion. The thermal oxide layer is located between the first gate and the semiconductor layer. The first CVD oxide layer is located between the first gate and the second gate. The gate oxide layer is generally located between the second gate and the semiconductor layer.
US09941356B1
A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.
US09941354B2
A semiconductor device includes a first gate trench and a second gate trench in a first main surface of a semiconductor substrate. A mesa is arranged between the first gate trench and the second gate trench. The mesa separates the first gate trench from the second gate trench. Each of the first and second gate trenches includes first sections extending in a first direction and second sections connecting adjacent ones of the first sections. The second sections of the first gate trench are disposed opposite to the second sections of the second gate trench with respect to a plane perpendicular to the first direction.
US09941352B1
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.
US09941345B2
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a scan line configured to transmit a scan signal and a data line crossing the scan line and configured to transmit a data voltage. The OLED display also includes a driving voltage line crossing a scan line and configured to transmit a driving voltage, a switching transistor connected to the scan and data lines, and a driving transistor connected to the switching transistor and including a driving gate electrode configured to function as a first storage electrode. The OLED display further includes a second storage electrode overlapping the first storage electrode and an expansion portion of the driving voltage line, an OLED electrically connected to the driving transistor and a blocking layer extending from the driving drain electrode and overlapping a portion of the data.
US09941344B2
Embodiments relate to an organic light emitting display device according to the present disclosure including: a plurality of pixels which includes red, white, blue, and green sub-pixels; driving transistor, each of which is disposed in each sub-pixel; and organic light emitting diodes, each of which is disposed corresponding to each sub-pixel, wherein a first step portion, first and second bank layers, and a first step compensation portion are disposed between the white sub-pixel and a sub-pixel adjacent thereto, thereby having an effect of suppressing a short circuit defect and a light leakage defect. In addition, an organic light emitting display device according to the present disclosure includes: red, white, blue, and green sub-pixels; at least one step portion between the sub-pixels; first and second bank layers; and a step compensation portion, thereby having an effect of suppressing a short circuit defect and a light leakage defect.
US09941339B2
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a plurality of pixels, each including a driving thin film transistor (TFT) formed over a substrate and including a driving gate electrode, a first storage capacitor comprising a first electrode and a second electrode, and a second storage capacitor comprising a third electrode and a fourth electrode. The first electrode is electrically connected to the driving gate electrode and the second electrode is formed over the first electrode and electrically insulated from the first electrode. The third electrode is electrically connected to the first electrode, is formed on a different layer from each of the first and second electrodes, and does not overlap the second electrode. The fourth electrode is formed over the third electrode and electrically insulated from the third electrode.
US09941338B2
An organic light-emitting diode display and a method of manufacturing the same are disclosed. In one aspect, the display includes a substrate including a display area configured to display an image and a peripheral area surrounding the display area. The display also includes a thin film transistor formed in the display area over the substrate, a first planarization layer covering the TFT in the display area, and an OLED formed over the first planarization layer and electrically connected to the TFT. The display also includes a second planarization layer formed in the peripheral area, the second planarization layer including a plurality of out-gassing holes formed therein, and at least a portion of the second planarization layer thinner than the first planarization layer.
US09941337B2
There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.
US09941336B2
The light emitting display device comprises: a substrate including a plurality of pixels that are arranged in a first direction and a second direction that crosses the first direction; a first electrode for each pixel on the substrate; a pixel defining layer on the substrate, the pixel defining layer having an opening for exposing the first electrode; a hole injection layer on the first electrode; a lyophilic pattern extending on the hole injection layer to cover the first electrode and the pixel defining layer that are on a same line in the first direction, and extending up to an outer region of outermost pixels of the plurality of pixels in the first direction; a hole transport layer on the lyophilic pattern; a light emitting layer on the hole transport layer; and a second electrode on the light emitting layer, wherein the lyophilic pattern includes a first lyophilic pattern having a plurality of grooves on one end portion thereof in the first direction and a second lyophilic pattern having a plurality of grooves on another end portion thereof in the first direction, and wherein the first lyophilic pattern and the second lyophilic pattern are alternately arranged in the second direction.
US09941335B2
A display device is provided. A display panel includes a display area and a pad area. A connector is connected to the pad area. A PCB is connected to the connector. A filling member is disposed between a side surface of the display panel and the connector.
US09941327B2
A detector module for detecting photons includes a detector formed from a semiconductive material, the detector having a first surface, an opposing second surface, and a plurality of sidewalls extending between the first and second surfaces, and a guard band coupled to the sidewalls, the guard band having a length that extends about a circumference of the detector, the guard band having a width that is greater than a thickness of the detector such that an upper rim segment of the guard band projects beyond the first surface of the detector, the upper rim segment being folded over a peripheral region of the first surface along the circumference of the detector, the guard band configured to reduce recombinations proximate to the edges of the detector.
US09941322B2
A semiconductor unit includes: a first device substrate including a first semiconductor substrate and a first wiring layer, in which the first wiring layer is provided on one surface side of the first semiconductor substrate; a second device substrate including a second semiconductor substrate and a second wiring layer, in which the second device substrate is bonded to the first device substrate, and the second wiring layer is provided on one surface side of the second semiconductor substrate; a through-electrode penetrating the first device substrate and a part or all of the second device substrate, and electrically connecting the first wiring layer and the second wiring layer to each other; and an insulating layer provided in opposition to the through-electrode, and penetrating one of the first semiconductor substrate and the second semiconductor substrate.
US09941320B2
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
US09941315B2
A photoelectric conversion device includes a photoelectric conversion unit including a first and second electrodes, a photoelectric conversion layer between the first and second electrodes, and an insulating layer between the photoelectric conversion layer and the second electrodes, an amplifier unit connected to the second electrode and outputs a signal generated in the photoelectric conversion unit, and a reset unit for resetting a voltage of the second electrode. An accumulating operation for accumulating signal charges in the photoelectric conversion unit and a charge removing operation for removing the signal charges from the photoelectric conversion unit are alternately executed in accordance with a voltage applied between the first and second electrodes, and the charge removing operation is executed multiple times between a first accumulating operation and a second accumulating operation which is executed after the first accumulating operation.
US09941312B2
The invention provides a manufacturing method for LTPS TFT substrate. After forming N+ areas on both sides of polysilicon layer, the first gate insulating layer, first gate, second gate insulating layer, and second gate are sequentially formed on polysilicon layer, and the second gate is wider than first gate to produce a low electric field region in the polysilicon layer to reduce leakage current; alternatively, forming first gate and first gate insulating layer, forming polysilicon layer and N+ areas on both sides of polysilicon layer, forming second gate insulating layer and second gate on polysilicon layer, the second gate insulating layer is thicker than first gate insulating layer and the second gate is wider than first gate, so that the second gate insulating layer sandwiched by the second gate beyond first gate and polysilicon layer is thicker and produces a smaller electric field, which simplifies process and reduce cost.
US09941307B2
A thin-film transistor (TFT) array substrate including: a first conductive layer selected from an active layer, a gate electrode, a source electrode, and a drain electrode of a TFT; a second conductive layer in a layer different from the first conductive layer; and a connection node coupling the first conductive layer to the second conductive layer. Here, the TFT array has a node contact hole formed by: a first contact hole in the first conductive layer; and a second contact hole in the second conductive layer, the second contact hole being integral with the first contact hole and not being separated from the first contact hole by an insulating layer, and at least a portion of the connection node is in the node contact hole.
US09941305B2
A pixel structure and a fabrication method thereof are provided, and the fabrication method includes steps as follows. A gate and a scan line connected to the gate electrode are formed on a substrate. An insulation layer is formed on the substrate and is patterned to form an opening corresponding to the gate electrode. A gate insulation layer is formed to cover the gate electrode and the scan line. A channel layer is formed on the gate insulation layer and is located in the opening. A first ohmic contact layer and a second ohmic contact layer are formed on the channel layer and are located in the opening. A source electrode, a drain electrode and a data line connected to the source electrode are formed on the first ohmic contact layer and the second ohmic contact layer. A first electrode is formed and is electrically connected to the drain electrode.
US09941303B1
The present application provides an array substrate, a display panel and a display device. The array substrate includes: a substrate; gate lines and data lines located on the substrate, intersecting and insulated from each other, which define a plurality of sub-pixel areas; the sub-pixel areas each comprises: a thin-film transistor; a pixel electrode, a barrier metal electrode. An orthographic projection of the drain electrode on the substrate is located between orthographic projections of two adjacent data lines on the substrate, an orthographic projection of the barrier metal electrode on the substrate is located between the orthographic projection of the drain electrode on the substrate and the orthographic projection of at least one of the two adjacent data lines on the substrate.
US09941298B2
Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.
US09941297B2
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
US09941284B2
A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an SRAM. In a memory cell of the SRAM, a load MOSFET is formed. An end of an active region extending in y-direction is arranged to gradually go away from a p-well as it goes from a gate electrode G2 side to a gate electrode G4 side in such a manner that a distance in x-direction between the end of the active region and the p-well is larger than a shortest distance in the x-direction between the p-well and the active region.
US09941283B2
A semiconductor device is provided. The semiconductor device includes a first fin-type pattern on a substrate, a first interlayer insulating layer on the substrate, covering the first fin-type pattern and including a first trench, the first trench intersecting the first fin-type pattern, a first gate electrode on the first fin-type pattern, filling the first trench, an upper surface of the first gate electrode being coplanar with an upper surface of the first interlayer insulating layer, a capping layer extending along the upper surface of the first interlayer insulating layer and along the upper surface of the first gate electrode, and a second interlayer insulating layer on the capping layer, the second interlayer insulating layer including a material different from that of the capping layer.
US09941279B2
A semiconductor structure includes a substrate, at least one active fin present on the substrate, and at least one isolation dielectric surrounding the active fin. The isolation dielectric has at least one trench therein. The semiconductor structure further includes at least one dielectric liner present on at least one sidewall of the trench of the isolation dielectric, and at least one filling dielectric present in the trench of the isolation dielectric.
US09941274B2
A semiconductor device includes at least one IGBT cell region, at least one switchable free-wheeling diode region, and at least one non-switchable free-wheeling diode region integrated in the same semiconductor substrate as the at least one IGBT cell region and the at least one switchable free-wheeling diode region.
US09941269B2
A drift region has a first conductivity type. A well region is at least partially included in an interface area, has an end portion between the interface area and an edge termination area, and has a second conductivity type. An extension region extends outward from the well region, is shallower than the well region, and has the second conductivity type. A plurality of field-limiting rings are provided outside the extension region in the edge termination area. Each of the field-limiting rings together with the drift region located on the inner side forms a unit structure. The field-limiting ring located closer to the outside has a lower proportion of a width to a width of the unit structure. The unit structure located closer to the outside has a lower average dose.
US09941268B2
Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode.
US09941264B2
In one embodiment, an overvoltage protection device may include a semiconductor substrate comprising an n-type body region. The overvoltage protection device may further include a first p-type region disposed in a first surface region of the semiconductor substrate, and forming a first P/N junction with the n-type body region, and a second p-type region disposed in a second surface region of the semiconductor substrate opposite the first surface, and forming a second P/N junction with the n-type body region, wherein the n-type body region, first p-type region, and second p-type region form a breakdown device having a breakdown voltage greater than 100 V when an external voltage is applied between the first surface region and second surface region.
US09941262B2
A laser liftoff process is provided. A device layer can be provided on a transfer substrate. Channels can be formed through the device layer such that devices comprising remaining portions of the device layer are laterally isolated from one another by the channels. The transfer substrate can be bonded to a target substrate through an adhesion layer. Surface portions of the devices can be removed from an interface region between the transfer substrate and the devices by irradiating a laser beam through the transfer substrate onto the devices. The laser irradiation decomposes the III-V compound semiconductor material. The channels provide escape paths for the gaseous products (such as nitrogen gas) that are generated by the laser irradiation. The transfer substrate is separated from a bonded assembly including the target substrate and remaining portions of the devices. The devices can include a III-V compound semiconductor material.
US09941255B2
A power semiconductor module includes: a positive arm and a negative arm that are formed by series connection of self-arc-extinguishing type semiconductor elements and that are connected at a connection point between the self-arc-extinguishing type semiconductor elements; a positive-side DC electrode, a negative-side DC electrode, and an AC electrode that are connected to the positive arm and the negative arm; and a substrate on which a wiring pattern is formed, the wiring pattern connecting the self-arc-extinguishing type semiconductor elements of the positive arm and the negative arm to the positive-side DC electrode, the negative-side DC electrode and the AC electrode. The positive-side DC electrode, the negative-side DC electrode, and the AC electrode are insulated from one another and arranged such that one of the electrodes faces each of the other two electrodes.
US09941244B2
In accordance with a method embodiment includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.
US09941239B2
In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.
US09941230B2
The present invention provides an electrical connecting structure between a substrate 21 and a semiconductor chip 22. The electrical connecting structure comprises a metal bump 26 formed on a contact pad 28 of a semiconductor chip 22 and a coating layer 25 formed on the metal bump 26 of the semiconductor chip 22. The coating layer includes material not wettable with solder. The electrical connecting structure further comprises a metal pad 24 formed on the substrate 21. The electrical connecting structure further comprises a solder 29 connecting to a side surface of the metal bump 26 and an outer surface of the metal pad 24. The outer surface is not covered by the coating layer 25.
US09941227B2
A package is provided. The package comprises a die and an impedance matching network. The die has a first terminal and a second terminal. The impedance matching network is coupled to the second terminal and comprises a first inductor and a first capacitor. The first inductor comprises first bond wire connections coupled between the second terminal and a first bond pad on the die, and second bond wire connections coupled between the first bond pad and a second bond pad coupled to the first capacitor.
US09941221B2
A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top surface of the bottom die, wherein the metal-particle-containing compound material comprises metal particles. A molding material molds at least a lower part of the bottom die therein, wherein the molding material is overlying the bottom substrate.
US09941214B2
Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.
US09941209B2
Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
US09941206B2
An interconnection structure includes an underlying layer including a lower interconnection, and an interlayered dielectric layer including a contact hole and a trench therein. The contact hole exposes a portion of the lower interconnection, and the trench extends along a first direction to be connected to the contact hole. A contact plug extends through the contact hole in the interlayered dielectric layer, and an upper interconnection line extends in the trench of the interlayered dielectric layer and connects to the contact plug. The contact plug includes lower and upper sidewalls inclined at first and second angles, respectively, relative to the underlying layer, and the second angle is less than the first angle. Related devices and fabrication methods are also discussed.
US09941204B2
An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region including a second metal structure; and a middle region located between the first end region and the second end region. In accordance with the present application, the middle region of the anti-fuse includes at least a portion of the second metal structure that is located in a gap positioned between a bottom III-V compound semiconductor material and a top III-V compound semiconductor material. A high-k dielectric material liner separates the second metal structure from a portion of the first metal structure.
US09941200B1
A first semiconductor substrate layer supports a first transistor including a first source-drain formed by a doped region of the substrate layer. A second semiconductor substrate layer supports a second transistor including a second source-drain formed by a doped region of the substrate layer. The second semiconductor substrate layer is stacked over the first semiconductor substrate layer and separated therefrom by an insulating layer. A metal wiring extends from an electrical contact with the doped region for the first source-drain, through the insulating layer and passing through an electrical isolation structure in the second semiconductor substrate layer to make an electrical contact with the doped region for the second source-drain. The electrical isolation structure is formed by one of a trench isolation or the doped region of the second source-drain itself. The isolation structure has a thickness equal to a thickness of the second semiconductor substrate layer.
US09941186B2
A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.
US09941185B2
A method and apparatus for a variable heat conductor that is able to increase heat conduction capacity based on operating temperature. The variable heat conductor is to be positioned between an electronic device and a heat sink to facilitate cooling of the electronic device. During cold start-up of the electronic device, the variable heat conductor acts as a thermal isolator, causing the electronic device to warm more quickly following the cold start-up. The variable heat conductor may fully conduct heat at higher temperatures that are at or above a desired temperature set-point.
US09941174B2
Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.
US09941170B2
A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.
US09941166B2
The invention relates to a method of processing a substrate, having a first surface with a device area and a second surface opposite the first surface, wherein the device area has a plurality of devices formed therein. The method comprises applying a pulsed laser beam to the substrate from the side of the second surface, in a plurality of positions along the second surface, so as to form a plurality of hole regions in the substrate, each hole region extending from the second surface towards the first surface. Each hole region is composed of a modified region and a space in the modified region open to the second surface. The method further comprises grinding the second surface of the substrate, where the plurality of hole regions has been formed, to adjust the substrate thickness.
US09941165B2
A semiconductor manufacturing method includes forming a first metal film on a semiconductor wafer by plating, ejecting liquid from a washer bar spaced from the wafer while rotating at least one of the washer and the semiconductor, and forming a second metal film on the first metal film. A plurality of nozzles are located on the washer bar and displaced from the position of the washer bar opposed to the center of the wafer, and a greater number of nozzles are adjacent the peripheral area of the semiconductor wafer than the central area of the semiconductor wafer. The nozzles in the peripheral area of the wafer eject the washing liquid in a direction inclined from the direction of the washer bar, and a nozzle arranged on the central area of the one main surface of the semiconductor wafer ejects the washing liquid towards the center position of the semiconductor wafer.
US09941162B1
Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.
US09941158B2
A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.
US09941150B1
A method for manufacturing a semiconductor device includes forming a plurality of stacked portions spaced apart from each other on a substrate, each of the plurality of stacked portions including a semiconductor fin, a dielectric layer on the semiconductor fin, and a polymer layer on the dielectric layer. The method also includes forming an inter-level dielectric layer on the substrate between the plurality of stacked portions, forming a doped region in the inter-level dielectric layer at a depth below a top surface of the inter-level dielectric layer, and recessing the inter-level dielectric layer down to the doped region to form a plurality of isolation regions between the plurality of stacked portions.
US09941149B2
The invention relates to a retaining system for handling substrate stacks, including a retaining surface for retaining a first substrate, and one or more recesses provided relative to the retaining surface, for retaining first magnetic bodies for securing the first substrate relative to a second substrate that is aligned with the first substrate. Second magnetic bodies are applied on a holding side of the second substrate.
US09941147B2
A transfer apparatus includes a supporting member, a free electron excitation device and a detection device; the free electrons excitation device is configured to excite semiconductor material of an object to be transferred to generate free electrons, and the detection device is configured to detect whether material of a surface of the transferred object in contact with the support surface of the supporting member is conductive under excitation by the free electron excitation device. A laser annealing apparatus comprising the transfer apparatus is further provided.
US09941141B2
Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
US09941140B2
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.
US09941132B2
A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion inside the stage; a heater inside the stage; a support portion which supports a conveyance carrier between a stage-mounted position on the stage and a transfer position distant from the stage upward; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage by lowering the support portion, application of voltage to the electrode portion is started in a state that the stage is being heated, and the plasma generation unit generates plasma after at least a part of an outer circumferential portion of a holding sheet holding the conveyance carrier contacts the stage and also after the heating of the stage is stopped.
US09941128B2
A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.
US09941127B2
A semiconductor includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a gate electrode. The gate electrode has a first portion arranged with the second semiconductor region in a direction perpendicular to a first direction extending from the first electrode to the first semiconductor region, and has a second portion on the first portion. The semiconductor also includes a gate insulating layer between the gate electrode and each of the three semiconductor regions. The gate insulating layer extends to the upper surface of the third semiconductor region to form an extending portion. The second portion of the gate electrode protrudes in an upward direction from the upper surface of the extending portion of the gate insulating layer, and a lower part of the second portion of the gate electrode is embedded in the first portion of the gate electrode.
US09941123B1
A method for etching features in a stack comprising a patterned hardmask over a carbon based mask layer is provided. A pattern is transferred from the patterned hardmask to the carbon based mask layer, comprising providing a flow of a transfer gas comprising an oxygen containing component and at least one of SO2 or COS, forming the transfer gas into a plasma, providing a bias of greater than 10 volts, and stopping the flow of the transfer gas. A post treatment is provided, comprising providing a flow of a post treatment gas comprising at least one of He, Ar, N2, H2, or NH3, wherein the flow is provided to maintain a processing pressure of between 50 mTorr and 500 mTorr inclusive, forming the post treatment gas into a plasma, providing a bias of greater than 20 volts, and stopping the flow of the post treatment gas.
US09941116B2
In this method for manufacturing a semiconductor element, a modified layer produced by subjecting a substrate (70) to mechanical polishing is removed by heating the substrate (70) under Si vapor pressure. An epitaxial layer formation step, an ion implantation step, an ion activation step, and a second removal step are then performed. In the second removal step, macro-step bunching and insufficient ion-implanted portions of the surface of the substrate (70) performed the ion activation step are removed by heating the substrate (70) under Si vapor pressure. After that, an electrode formation step in which electrodes are formed on the substrate (70) is performed.
US09941112B2
Provided is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked.
US09941109B2
A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned.
US09941107B2
A method and apparatus are disclosed for improving resolution and duty-cycle of a multi-reflecting TOF mass spectrometer (MR-TOF) by arranging a cylindrical analyzer having an appropriate radial deflection means, means for limiting ion divergence in the tangential direction and a pulsed source providing ion packet divergence of less than 1 mm*deg. There are disclosed embodiments for fifth-order focusing cylindrical ion minors. Separate embodiments provide parallel tandem MS-MS within a single cylindrical MR-TOF.
US09941103B2
A bias-variant photomultiplier tube (PMT) includes a photocathode that when operating absorbs photons and emits photoelectrons responsive to the absorbed photons. The bias-variant PMTO also includes a plurality of dynodes that receive the photoelectrons emitted by the photocathode. The plurality of dynodes include a first pair of dynodes having a first bias difference and at least a second pair of dynodes having a second bias difference. The second bias difference is greater than the first bias difference. The bias-variant PMTO also includes an anode to receive photoelectrons directed from the plurality of dynodes.
US09941102B2
Work piece processing is performed by pulsed discharges between an anode (2) and a magnetron sputtering cathode (1) in solid-gas plasmas using a chamber (2) containing the work piece (7). A system (12) maintains a vacuum in the chamber and another system (14) provides sputtering and reactive gases. The pulses are produced in a plasma pulser circuit including the anode and the cathode, the discharges creating gas and partially ionized solid plasma blobs (3) moving or spreading from a region at a surface of the cathode towards the work piece and the anode. A pulsed current comprising biasing pulses arises between the second electrodes. Biasing discharges are produced between the anode and the work piece when said plasma blobs have spread to regions at the anode and at the work piece so that the pulsed current is the current of these biasing discharges.
US09941093B2
The invention relates to a target processing unit (10) comprising a vacuum chamber (30) for accommodating a target to be processed, a projection column (46) within the vacuum chamber for generating a beam and projecting the beam towards the target, and a first conduit arrangement (26,36,37,60) for connecting the projection column to external equipment (22). The vacuum chamber can comprise a positioning system (114) for supporting the target, and a second conduit arrangement (110) distinct from the first conduit arrangement for connecting the positioning system to external equipment, wherein the positioning system is moveably arranged with respect to the projection column, and wherein the positioning system and the projection column occupy spatially distinct portions of the vacuum chamber. The first conduit arrangement extends through an upper side of the vacuum chamber, and the second conduit arrangement extends through a lower side of the vacuum chamber.
US09941090B2
Disclosed herein are a high-voltage generator for an x-ray source, an x-ray gun, an electron beam apparatus, a rotary vacuum seal, a target assembly for an x-ray source, a rotary x-ray emission target, and an x-ray source. These various aspects may separately and/or together enable the construction of an x-ray source which can operate at energies of up to 500 kV and beyond, which is suitable for use in commercial and research x-ray applications such as computerised tomography. In particular, the high-voltage generator includes a shield electrode electrically connected intermediate of a first voltage multiplier and a second voltage multiplier. The electron beam apparatus includes control photodetectors and photo emitters having a transparent conductive shield arranged therebetween. The rotary vacuum seal includes a pumpable chamber at a position intermediate between high-pressure and low-pressure ends of a bore for a rotating shaft. The rotary target assembly is configured such that when a torque between a bearing housing and a vacuum housing exceeds a predetermined torque, the bearing housing rotates relative to the vacuum housing. The rotary x-ray emission target has a plurality of target plates supported on a hub, the plates being arranged on the hub to provide an annular target region about an axis rotation of the hub. The x-ray gun is provided with a shield electrode maintained at a potential difference relative to the x-ray target different to the electron beam emission cathode.
US09941086B2
Provided is a fusible link unit (electrical component unit) including a fusible link (electrical component), a battery terminal fixed to an electrode post (electrode) of a battery, and a support member formed as a different body from the battery terminal and fixed to the battery, the support member supporting the fusible link (electrical component), in which the fusible link (electrical component) includes a main link body (main electrical component body) and a power supply terminal made of conductive metal to be exposed from the main link body (main electrical component body) and electrically connected to the electrode post (electrode) through the battery terminal, and the support member supports the main link body (main electrical component body) such that the main link body extends in an orthogonal direction substantially orthogonal to an installation surface portion.
US09941083B2
A pressure switch is disclosed. The pressure switch includes a housing and a pressure-receiving chamber that communicates with a duct to which an operating pressure is supplied. The pressure switch also includes a diaphragm assembly with a diaphragm that is displaced in response to a pressure inside the pressure-receiving chamber. The pressure switch also includes a movable contact that comes into contact with a fixed contact accommodated in a center portion of an inside of the housing when the pressure inside the pressure-receiving chamber is above a certain value. One of the movable contact and the fixed contact has radially diverging contact faces that are arranged such that contact between the fixed contact and the moveable contact can be established with at least two of the radially diverging contact faces at the same time.
US09941076B2
An illuminated keyboard device includes plural keys, plural light-emitting elements and a membrane switch circuit module. Each key includes a keycap and an elastic element. Each elastic element has a protrusion. The plural elastic elements are located over plural contacts of the membrane switch circuit module and connected with the plural keycaps. The plural light-emitting elements are located under the corresponding elastic elements. Moreover, the protrusions within the elastic elements and the contacts of the membrane switch circuit module are all ring-shaped structures, and each light-emitting element is aligned with the center region of the corresponding contact of the membrane switch circuit module. Consequently, while the protrusion is moved downwardly to push the corresponding contact, a corresponding key signal is generated.
US09941057B2
A thermal transfer device for generating a thermal transfer between an energy store and a temperature-control panel for the temperature-control of the energy store. The thermal transfer device has a thermal insulation layer made of an unevenly distributed insulation material and a tolerance compensating layer made of a compressible material for compensating different material strengths of the thermal insulation layer.
US09941048B2
A chargeable communication module is provided, which includes: a wireless power charging coil; a wireless communication coil being electrically isolated from the wireless power charging coil; and a magnetic body. The wireless power charging coil is disposed on a surface of the magnetic body. The wireless communication coil is arranged adjacent to and outside of the wireless power charging coil. At least a portion of the wireless communication coil is disposed on the surface of the magnetic body.
US09941047B2
A shield for a toroidal transformer that includes a toroidal assembly that comprises a toroidal magnetic core and a first winding includes a sheet of flexible non-magnetic conductive material. The sheet of flexible non-magnetic conductive material comprises a trunk portion extending along a longest dimension of the sheet of flexible non-magnetic conductive material and configured to wrap along an outer dimension of the toroidal assembly, and a plurality of fingers extending outwardly from the trunk portion and configured to wrap around portions of the first winding along portions of sides of the toroidal assembly in a direction towards the center of the toroidal magnetic core and folding into an inner dimension of the toroidal assembly.
US09941046B2
A circuit arrangement for reducing unidirectional flux component in a transformer core includes a compensation winding magnetically coupled to the transformer core, a transductor series connected with the compensation winding in a compensation current path, wherein the compensation current path has two parallel branches each containing a power winding of the transductor and an uncontrolled valve connected in series, where flow directions of the valves run counter to one another, and where each power winding is magnetically coupled to a control winding via a saturable transductor core, and includes a controller to which a detector supplies magnitude and direction information of the unidirectional flux component, and which generates a control variable supplied to each control winding such that the saturation state of the transductor core is variable such that a compensation current is formed in the compensation current path that counteracts the unidirectional flux component in the transformer core.
US09941044B2
An insulation type step-down converter includes first and second step-down transformers each of which includes an input-side coil and an output-side coil. An intermediate portion of the output-side coil of the first step-down transformer and an intermediate portion of the output-side coil of the second step-down transformer are connected to each other. First, second, third, and fourth rectifier elements are connected in series with first, second, third, and fourth output-side coils, respectively. Smoothing coils are connected to the first to fourth output-side coils. The first, second, third, and fourth rectifier elements are connected such that electric currents flow simultaneously in the first output-side coil and the third output-side coil, and electric currents flow simultaneously in the second output-side coil and the fourth output-side coil in a manner alternating with the electric currents in the first output-side coil and the third output-side coil.
US09941041B2
An electromechanical assembly is provided controlled by voltage across a motor or with an electronic system. The electromechanical assembly includes a control circuit coupled to sense voltage at the motor or within the electronic system, and an electromechanical actuator energized by the voltage sensed by the control circuit. A movable element is movable by the electromechanical actuator from an operational position to a quiesced position when the voltage sensed by the control circuit falls below a quiesced threshold. In certain embodiments, the voltage being sensed is across a motor of an air-moving assembly, which resides within a support structure, or the voltage being sensed is within the electronic system, which resides within the support structure, and the movable element is an interlock element which interlocks to the support structure to prevent removal of one or more components from the structure when sensed voltage is above the quiesced threshold.
US09941040B2
A soft magnetic core is provided, in which permeabilities that occur at least two different locations of the core are different. A method for producing a soft magnetic core that has different permeabilities at at least two different locations is also provided.
US09941039B2
A soft magnetic member is formed such that, when a differential relative permeability in an applied magnetic field of 100 A/m is represented by a first differential relative permeability μ′L, and when a differential relative permeability in an applied magnetic field of 40 kA/m is represented by a second differential relative permeability μ′H, a ratio of the first differential relative permeability μ′L to the second differential relative permeability μ′H satisfies a relationship of μ′L/μ′H≤10, and a magnetic flux density in an applied magnetic field of 60 kA/m is 1.15 T or higher.
US09941033B2
A method and system for manufacturing a superconducting material is described. In one embodiment, a layer of refractory cushion is placed over a spool. A first layer of superconducting cable is wound over the first layer of refractory cloth. The superconducting cable is reaction heat-treated on the spool. A first layer of refractory fabric can be placed over the layer of refractory cushion. One or more adjustment mechanisms can be disposed between the first layer of the superconducting cable and the spool.
US09941028B2
An electrical conductor has at least one conducting strand made up at least of a layer of copper and of a layer of silvered copper alloy, in which the silver content by mass is between 0.1% and 0.5%.
US09941027B2
The invention relates to a method for producing a radioisotope, which method comprises irradiating a volume of radioisotope-precursor fluid contained in a sealed cell of a target using a beam of particles of a given current, which beam is produced by a particle accelerator. The target is cooled and the internal pressure in the sealed cell is measured. During the irradiation, the internal pressure (P) in the sealed cell is allowed to vary freely. The irradiation is interrupted or its intensity is reduced when the internal pressure (P) in the sealed cell departs from a first tolerated range defined depending on various parameters that influence the variation in the internal pressure in the sealed cell during the irradiation. These parameters for example comprise, for a given target, particle beam and radioisotope-precursor fluid: the degree of filling of the hermetic cell, the cooling power used to cool the given target, and the beam current (I). The invention also relates to an installation for implementing the method.
US09941024B2
In one embodiment, a fusion reactor includes two internal magnetic coils suspended within an enclosure, a center magnetic coil coaxial with the two internal magnetic coils and located proximate to a midpoint of the enclosure, a plurality of encapsulating magnetic coils coaxial with the internal magnetic coils, and two mirror magnetic coil coaxial with the internal magnetic coils. The fusion reactor further includes one or more electromagnetic wave generators operable to inject a beam of electromagnetic waves into the enclosure.
US09941023B2
Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.
US09941018B2
A gate driving circuit and a display device using the same are discussed. The gate driving circuit according to an embodiment includes a first shift register configured to sequentially shift a gate start pulse in response to a gate shift clock and output a gate pulse shifted on a per block basis, each block including a plurality of gate lines, a second shift register configured to sequentially shift the gate start pulse in response to the gate shift clock and output a gate pulse shifted on a per gate line basis, and a controller configured to supply the gate shift clock to one of the first and second shift registers.
US09941014B2
A nonvolatile memory device includes a memory cell array having a normal area and a temporary area. A page buffer stores data to be written to the normal area in a normal program operation and store a temporary data to be written to the temporary area in a temporary program operation. A control logic performs the normal program operation including a plurality of program loops. The control logic receives a suspend command before the normal program operation is completed and determines, in response to the suspend command, whether to complete the normal program operation or to suspend the normal operation and perform the temporary program operation based on a reference value representing a time for performing at least one program loop of the plurality of program loops.
US09941004B2
An arming switch structure and method of operation. The arming switch is integrated with a reactive material erasure device and phase change memory cell array and is coupled to a tamper detection device configured to trigger a signal for conduction to the reactive material erasure device that generates heat and induces a phase change in the phase change memory cell array. Prior to packaging, the memory chip is “armed” in a high-resistance state to prevent conduction of any signal to the reactive material erasure device. After the memory chip is packaged, the Reactive Material can be “disarmed” at a chosen time or condition by applying a bias to the arming switch activation layer, thereby heating and crystallizing the arming switch material, placing it in a low resistance state. In the disarmed state, the arming switch may conduct the trigger signal from tamper detection device to the reactive material erasure device.
US09940987B2
A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.
US09940962B2
In some embodiments, a thermally assisted data recording medium has a recording layer formed of iron (Fe), platinum (Pt) and a transition metal T selected from a group consisting of Rhodium (Rh), Ruthenium (Ru), Osmium (Os) and Iridium (Ir) to substitute for a portion of the Pt content as FeYPtY-XTX with Y in the range of from about 20 at % to about 80 at % and X in the range of from about 0 at % to about 20 at %.
US09940960B2
A slider design for a hard disk drive (HDD) features an air-bearing surface (ABS) topography with arrays of micro-dots formed on bases of a multiplicity of cavities at different depths. The design eliminates the accumulation of hydrocarbons (e.g., spindle oil and disk lubricant) deposits in regions of air stagnation within the cavities where backflows and foreflows of air meet and cancel during HDD operation. The micro-dots are small raised regions of various shapes having sizes and spacings in the range between 2 and 100 microns and, in a preferred embodiment, heights of 0.15 microns above the cavity bases.
US09940952B2
A method according to one embodiment includes measuring an initial coating thickness on a tape bearing surface of a module in a carrier, running a tape across the tape bearing surface, and at intervals, measuring a residual thickness of the coating.
US09940949B1
In a speech-based system, a wake word or other trigger expression is used to preface user speech that is intended as a command. The system receives multiple directional audio signals, each of which emphasizes sound from a different direction. The trigger expression is detected in an individual directional audio signal by comparing a confidence score with a confidence threshold. An individual confidence threshold is specified for each directional audio signal. The confidence thresholds are adjusted during operation of the system based on performance information that is generated during operation of the system. As an example, performance information may include the number of times that the trigger expression has been detected in each of the directional audio signals.
US09940948B2
Described is a computer-implemented method performed in connection with a computerized system incorporating an audio capture device, a central processing unit, a display device and a memory, the computer-implemented method involving: capturing an audio signal using the audio capture device; using the central processing unit to analyze the captured audio signal; when the audio signal satisfies a predetermine criterion, using the central processing unit to generate a hash of the captured audio signal; finding a similar audio signal hash among a plurality of stored audio signal hashes; and identifying a device associated with the captured audio signal using the found similar audio signal hash.
US09940940B2
An encoding method and encoder is provided for transparent lossless audio watermarking by quantizing an original PCM audio signal twice, each quantization quantizing to a quantization grid. As a PCM signal is inherently already quantized, there are three quantization grids to consider, the first being the quantization grid of the original PCM signal, the second being that of the watermarked signal and the third being that of an intermediate signal. The technique reduces the amount of introduced quantization error, spectrally shapes the error and fully decorrelates signal alterations from the original audio, thus making the error more similar to additive noise. A decoding method and decoder is also provided, as is a method of altering the watermark without fully decoding the encoded signal.
US09940938B2
An audio decoder for providing at least four audio channel signals on the basis of an encoded representation is configured to provide a first residual signal and a second residual signal on the basis of a jointly encoded representation of the first residual signal and of the second residual signal using a multi-channel decoding. The audio decoder is configured to provide a first audio channel signal and a second audio channel signal on the basis of a first downmix signal and the first residual signal using a residual-signal-assisted multi-channel decoding. The audio decoder is configured to provide a third audio channel signal and a fourth audio channel signal on the basis of a second downmix signal and the second residual signal using a residual-signal-assisted multi-channel decoding. An audio encoder is based on corresponding considerations.
US09940937B2
This disclosure describes techniques for coding of higher-order ambisonics audio data comprising at least one higher-order ambisonic (HOA) coefficient corresponding to a spherical harmonic basis function having an order greater than one. This disclosure describes techniques for adjusting HOA soundfields to potentially improve spatial alignment of the acoustic elements to the visual component in a mixed audio/video reproduction scenario. In one example, a device for rendering an HOA audio signal includes one or more processors configured to render the HOA audio signal over one or more speakers based on one or more field of view (FOV) parameters of a reference screen and one or more FOV parameters of a viewing window.
US09940935B2
A method is performed at a device having one or more processors and memory. The device establishes a first-level Deep Neural Network (DNN) model based on unlabeled speech data, the unlabeled speech data containing no speaker labels and the first-level DNN model specifying a plurality of basic voiceprint features for the unlabeled speech data. The device establishes a second-level DNN model by tuning the first-level DNN model based on labeled speech data, the labeled speech data containing speech samples with respective speaker labels, wherein the second-level DNN model specifies a plurality of high-level voiceprint features. Using the second-level DNN model, registers a first high-level voiceprint feature sequence for a user based on a registration speech sample received from the user. The device performs speaker verification for the user based on the first high-level voiceprint feature sequence registered for the user.
US09940934B2
An adaptive voice authentication system is provided. The adaptive voice authentication system includes an adaptive module configured to compare a feature quality index of the plurality of authentication features and the plurality of enrollment features and dynamically replace and store one or more enrollment features with one or more authentication features to form a plurality of updated enrollment features. The adaptive module is configured to generate an updated enrollment voice print model from the plurality of the updated enrollment features. The adaptive module is further configured to compare the updated enrollment voice print model with the previously stored enrollment voice print model and dynamically update the previously stored enrollment voice print model with the updated enrollment voice print model based on a model quality index.
US09940933B2
A speech recognition method includes receiving a sentence generated through speech recognition, calculating a degree of suitability for each word in the sentence based on a relationship of each word with other words in the sentence, detecting a target word to be corrected among the words in the sentence based on the degree of suitability for each word, and replacing the target word with any one of candidate words corresponding to the target word.
US09940930B1
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for securing audio data. In one aspect, a method includes restricting access by the device to audio information detected by a microphone, receiving data indicating that the device is authorized to access audio information detected by the microphone during a limited period of time, and in response to receiving data indicating that the device is authorized to access audio information detected by the microphone during the limited period of time, providing audio information to the device. The method also includes monitoring audio information detected by the microphone during the limited period of time for the presence of a hotword and after the end of the limited period of time, restricting access by the device to audio information detected by the microphone.
US09940927B2
In some aspects, a method of recognizing speech that comprises natural language and at least one word specified in at least one domain-specific vocabulary is provided. The method comprises performing a first speech processing pass comprising identifying, in the speech, a first portion including the natural language and a second portion including the at least one word specified in the at least one domain-specific vocabulary, and recognizing the first portion including the natural language. The method further comprises performing a second speech processing pass comprising recognizing the second portion including the at least one word specified in the at least one domain-specific vocabulary.
US09940906B2
A write circuit of a storage device, in a first mode, writes a plurality of first pixel data units, each of the first pixel data units being constituted by data for pixels that are on the same data line and on different scan lines in a display panel, into a plurality of memory cells connected to a selected word line, and in a second mode, writes a plurality of second pixel data units, each of the second pixel data units being constituted by data for pixels that are on the same scan line and on different data lines in the display panel, into a plurality of memory cells connected to a selected word line.
US09940903B2
Apparatus and methods for managing, manipulating and presenting data objects within a graphical user interface with variable dimensions, shapes, locations and interactions. The apparatus and methods allow for variable data objects to be both pinned and liquid depending on a larger management and manipulation apparatus. The apparatus consists of databases that store the data objects to be displayed within the user interface and the layout coordinates, variable potential object size, and whether the object can move or not based on the graphical user interface dimensions. The object manipulations include the representation of such objects on the graphical user interface in a defined sequence.
US09940897B2
A method for sharing a mixed reality experience (mixed reality content, mixed reality event) between one or more computing devices is disclosed. The method includes: determining a spatial location and a spatial orientation (spatial data) of the one or more computing devices each having a camera; mapping the (spatial) location and/or the spatial orientation (spatial data) of each of the one or more computing devices into a mixed reality manager; and presenting an event that is shared among the one or more computing devices, and, the presenting of the event is experienced simultaneously and varies among each of the one or more computing devices depending on the location or the orientation or both.
US09940893B2
A head mounted device control method includes capturing situation data, using the situation data to determine whether a wearer of a head mounted device is inside a moving vehicle, and when it is determined that the wearer is inside a moving vehicle, controlling an image capture apparatus in the head mounted device to capture an environmental image, using the captured environmental image to determine whether a seat taken by the wearer is a driver's seat, and when it is determined that the seat taken by the wearer is the driver's seat, disabling a preset service, where the preset service includes a screen display service of a near-eye display. The method may reduce diversion of attention of the wearer, and improve driving safety.
US09940890B2
Provided is a liquid crystal display device, including: a plurality of scanning connection lines formed on at least one side of edges of the image display region, the plurality of scanning connection lines connecting together a scanning signal drive circuit and a plurality of scanning signal lines; a selection circuit formed so as to be interposed between the plurality of scanning connection lines and the plurality of scanning signal lines, the selection circuit being configured to selectively short-circuit one of a plurality of the scanning signal lines to one of the plurality of scanning connection lines based on a selection signal; and a selection signal line connected to the selection circuit, the selection signal line transmitting the selection signal to the selection circuit.
US09940876B2
A display device including a display area including a plurality of pixel circuits, a peripheral area including a scanning circuit, a plurality of first scanning lines, a plurality of second scanning lines, and a plurality of third scanning lines. Each of the plurality of pixel circuits includes a write transistor, a drive transistor, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a capacitor, and a light emitting element. Duration of a light emitting period of respective light emitting element in each of the pixel circuits within one frame period is variably controlled by changing a width of an input pulse.
US09940874B2
The present disclosure provides a pixel compensating circuit. The circuit includes a driving module and a resetting module connected to a reference voltage line for providing an initial potential and a reset-control potential, a scanning signal line, and the driving module. The circuit further includes a data-writing module connected to a data signal line, the scanning signal line, and the driving module.
US09940870B2
An image processing unit includes: a gain calculating section obtaining, based on first luminance information for each pixel, a first gain, in which the first gain is configured to increase with an increase in pixel luminance value in a range where the pixel luminance value is equal to or larger than a predetermined luminance value, and in which the pixel luminance value is derived from the first luminance information; and a determination section determining, based on the first luminance information and the first gain, second luminance information for each of the pixels.
US09940869B2
A display device includes a display panel and a display driver driving the display panel. The display driver is connected to a host with a clock lane and at least one a data lane. The display driver includes: an interface circuit configured to receive an external clock signal from the host via the clock lane, receive a data signal from the host via the data lane, and output reception data transmitted over the data signal; a control circuit configured to output an internal clock signal synchronous with the external clock signal; and a drive circuitry configured to drive the display panel in response to image data included in the reception data in synchronization with the internal clock signal fed from the control circuit. The control circuit is configured to feed the internal clock signal in response to a type of a reception packet included in the reception data.
US09940864B2
There is provided a display device that is capable of suppressing occurrence of brightness drop which is caused by refresh of a display image during pause driving. In a normal driving mode, input image data (SsD0) according to a continuous tone method is supplied to a source driver (310) through a data selector (230) as an image signal (SsD) for driver. On the other hand, in a low-frequency driving mode in which pause driving is performed, the input image data (SsD0) is converted into dithered input image data (SsD1) by a dithering processing circuit (220), and is supplied to the source driver (310) through the data selector (230) as the image signal (SsD) for driver. A gradation of the dithered input image data (SsD1) is represented in a pseudo manner by an area coverage modulation method by using two values of a maximum value and a minimum value that can be taken as the gradation value of the input image data (SsD0).
US09940860B2
A display device includes a pixel array, a switch element, and inspection lines. In a display area, at least a portion of an outer region includes a curved section and pixels to which a data line is connected are disposed. The switch element is disposed in a bezel area outside the display area, and supplies a test voltage to the data line in response to an enable signal. The inspection lines connect an inspection pad part and switch elements and are disposed in a staircase form along the curved section. The switch elements are disposed along the inspection lines and include first and second switch elements disposed to be adjacent to each other in a direction perpendicular to each other.
US09940849B2
A surgical simulation system is provided. The system includes at least one simulated body organ placed upon the base of an organ tray and at least one covering layer placed over the simulated body organ. At least one of the simulated body organ and covering layer includes electro-conductive gel that is operably severable under application of electrical current to simulate electrosurgery in a training environment. The training environment comprises a top cover connected to and spaced apart from a base to define an internal cavity that is partially obstructed from direct observation by a practitioner. The tray, simulated body organs and covering layer are placed inside the internal cavity for the practice of laparoscopic surgical procedures.
US09940848B1
Methods, computer-readable media, software, and apparatuses provide a tool for use by drivers and/or coaches throughout the pre-license stage of obtaining a driver's license. A pre-license program may control a computing device to collect drive data while a driver is driving a vehicle. This drive data may be used to detect a drive event. Then, the computing device may present coaching information associated with the detected drive event. The coaching information may provide a passenger, such as a coach or parent, with real-time advice for instructing the driver how to improve his/her driving skills. Moreover, the drive data collected may be used to prepare reports providing feedback to the drivers and coaches.
US09940847B1
A virtual reality exercise device including : at least one actuator; at least one of a handle, a foot stirrup, a step, and a limb strap, where the at least one actuator is coupled to the at least one of a handle, a foot stirrup, a step, and a limb strap, where the actuator is designed to provide resistance force to at least one motion carried out by the user; a computer processor; computer readable non-transitory medium coupled in communication with the computer processor; an actuator control circuit coupled in communication to the computer processor and adapted to receive signals from the computer processor and output the signals to control the at least one actuator; a software algorithm stored on the computer readable non-transitory medium, where the computer processor executes the software algorithm, where the computer processor outputs a signal that is at least partially used by the actuator control circuit to control the at least one actuator; a virtual reality display coupled in communication to the processor, wherein the virtual reality display is adapted to create a visual display for the user, wherein the communication between the processor and the virtual reality display is adapted to synchronize the force output of the at least one actuator and the virtual reality display. The virtual reality exercise device is preferably designed to provide variable, interactive, and immersive exercises that include force the follows along with either real world physical activities, or fantasy activities, while at the same time providing physical exercise for the user. There may, however, be any suitable use for the virtual reality exercise device.
US09940842B2
Concepts and technologies disclosed herein are directed to intelligent drone traffic management via a radio access network (“RAN”). As disclosed herein, a RAN node, such as an eNodeB, can receive, from a drone, a flight configuration. The flight configuration can include a drone ID and a drone route. The RAN node can determine whether capacity is available in an airspace associated with the RAN node. In response to determining that capacity is available in the airspace associated with the RAN node, the RAN node can add the drone ID to a queue of drones awaiting use of the airspace associated with the RAN node. When the drone ID is next in the queue of drones awaiting use of the airspace associated with the RAN node, the RAN node can instruct the drone to fly through at least a portion of the airspace in accordance with the drone route.
US09940838B2
Negotiating a multi-vehicle environment using vehicle-to-vehicle network tokens for intra-vehicle communication. Preliminary routing assignments are efficiently improved by available intra-vehicle communication.
US09940835B2
A method, system and computer program product for dynamically routing messages in a publish/subscribe system. A messaging application receives messages from sensors (e.g., road condition sensors). Upon analyzing the messages using data analytics, an event (e.g., icy road condition) may be correlated with the analyzed messages. In such a scenario, a temporal topic based on the triggered event is created. Furthermore, a temporal publication (e.g., “icy road condition near exit 40”) and a temporal subscription are created. Potential subscribers to be associated with the temporal subscription are identified by using either geo-location information or social media information. Once those subscribers are identified, they are associated with the temporal subscription. The temporal publication is then published to the subscribers associated with the temporal subscription. In this manner, messages are dynamically routed to the appropriate subscribers that may have previously been excluded based on dynamically created temporal topics, subscriptions and publications.
US09940830B2
A wireless switch assembly, comprising: a wireless switch comprising a control switch; a wireless transmitter connected to the control switch and transmitting a corresponding control signal according to the instruction of the control switch; a first identification card pluggably mounted in the wireless switch and connected to the wireless transmitter; a wireless receiver connected to a controller of a controlled piece and communicating with the wireless switch through radio frequency signal or optical signal. The wireless receiver has a second identification card pluggably mounted therein. The present invention can achieve a remote control by a low power consumption wireless transceiver module and matches the wireless switch to the wireless receiver via the identification cards, thus eliminating the need for complicated control wiring, therefore greatly reducing the complexity of wiring, saving electric wires and cables, and reducing cost.
US09940828B2
A home appliance control method and device are provided. The method includes: receiving operation mode information from a home appliance, wherein the operation mode information indicates a current operation mode of the home appliance; and sending the operation mode information to another home appliance to cause said another home appliance to operate in the indicated operation mode. Accordingly, a wearable device can receive from a home appliance operation mode information, and then send the same to another home appliance to cause said another home appliance to operate in the operation mode of the home appliance.
US09940824B2
Systems and methods of self-monitoring notification appliances are provided. A self-monitoring notification appliance can include a notification device and a monitoring sensing device. The notification device can produce one or more signals, and the monitoring device can sense a visual and/or acoustic characteristic of the one or more signals to determine successful operation thereof.
US09940823B2
An emergency method, system, and non-transitory computer readable medium include a detection device configured to detect an emergency situation and switch a first device to emergency mode, an emergency mode device configured to gather information regarding the emergency situation while the first device is in emergency mode, and an actuation and discovery device configured to discover a second device in a vicinity of the first device and actuate the second device to perform an action based on the emergency situation detected by the detection device.
US09940814B1
An apparatus for an embedded sensor cable assembly, where a first cable assembly includes a cable portion and a connector portion. The cable portion includes a first embedded sensor and a second embedded sensor, where the first embedded sensor is electrically coupled to the second embedded sensor and where the first embedded sensor and the second embedded sensor is capable of registering orientation measurements. A microcontroller is electrically coupled to the connector portion, first embedded sensor and the second embedded sensor, where the microcontroller is capable of receiving the orientation measurements from the first embedded sensor and the second embedded sensor.
US09940799B2
A fence alarm, having a plurality of laterally spaced electrically conductive fence elements, the fence elements electrically being connected in series with each other, a sensing arrangement electrically connected to the plurality of conductive fence elements, the sensing arrangement being calibrated to a nominal electrical value, the sensing arrangement further being operable to sense a predefined deviation from the nominal electrical value caused by a deviation in an electrical property of the conductive fence elements.
US09940798B2
A magnet and magnetometer may be integrated into a smart home environment and allow it to be placed into an away mode of operation despite an entry point being semi-open. The disclosed implementations can detect a magnetic field strength and determine, based on the detected field strength, an approximate distance that a moveable partition is open. In some configurations, the presence of a second magnetic source can be detected. A notice may be generated based on one or more signals received from the magnetometer. The notice may be sent to a controller, a remote system, a remote device, and/or a client device as disclosed herein.
US09940784B2
An apparatus and method for a game of play for use in a casino establishment, or on a general purpose computing device for offering games with multiple outcomes and including blockading game elements or symbols. A base game, or an outcome on a base game that triggers a sub-game or a bonus game involves forming winning combinations from combinations of symbols in a matrix using only accessible symbol positions. Achieving winning combinations of symbols among accessible symbols results in awards to players. The apparatus and method are offered on electronic gaming machines such as slot machines and video poker machines, but may also be deployed on other devices such as on a general purpose computing device or mobile phone in stand-alone form or connected to a network, such as the internet.
US09940780B2
A system for interactive gaming among a plurality of players includes a host computer system and a plurality of player terminals communicably coupled to the host computer system or gaming platform via a network. The plurality of player terminals may be located at a plurality of licensed gaming locations. The plurality of player terminals may be configured to engage the plurality of players in a common interactive game operated by the host computer system. The plurality of player terminals can include means for dispensing player winnings from the player terminal.
US09940766B2
Lock arrangement and method for detecting the presence and location of a device sending a radio signal, which lock arrangement includes a lock case that can be fixed into a door, which lock case includes a locking latch and a latch mechanism. The lock arrangement further includes at least two antennas fitted into connection with the lock arrangement and a device for receiving radio signals connected to the antennas. The lock arrangement is able to determine on the basis of the signals measured from the antennas on which side of the lock arrangement the device sending a radio signal is located.
US09940762B2
A vehicle computing system having a computer processor in communication with a wireless transceiver, such that the wireless transceiver is capable of communication with a wireless communication device located remotely from the processor. The computer processor may be configured to receive input identifying at least one checksum value from one or more modules in the vehicle. The computer processor may transmit the at least one checksum value to a remote server through the wireless communication device. The remote server may compare the at least one checksum value to a predetermined value. Based on the compared results, the processor may receive one or more messages from the remote server to indicate whether the at least one checksum is equal to the predetermined value. The processor may generate one or more remedial actions if the at least one checksum is not equal to the predetermined value.
US09940756B2
An object-image alignment data generating method for use in an object recognition system is presented. The method obtains a 3D model and a set of 2D images of the object. Each 2D image from the set is captured based on a particular camera point of view. The method then uses the 3D model of the object to generate multiple silhouettes of the object according to different camera point of views. Each silhouette is then matched and aligned with a 2D image based on the corresponding camera point of view. The method also derives at least one descriptor from the 2D images and compiles feature points that correspond to the descriptors. Each feature point includes a 2D location and a 3D location. The method then generates an object-image alignment packet by packaging the 2D images, the descriptors, and the feature points.
US09940746B2
Disclosed are systems, methods, devices and computer-readable mediums for image fetching for timeline scrubbing of digital media. In some implementations, a method comprises: receiving at a first time prior to receiving a scrub command, a first set of scrub images associated with digital media, the first set of scrub images having a first set of positions on a timeline of the digital media; receiving a first scrub command; receiving at a second time after the first time, a second set of scrub images associated with the digital media, the second set of scrub images having a second set of positions on the timeline that fill time gaps in the first set of positions on the timeline; animating, a timeline overlay including the timeline, a playhead and a scrub image window; and selecting a scrub image from the first or second sets of scrub images for presentation in the scrub image window.
US09940744B2
Remote font management techniques are described. In one or more implementations, one or more layout tables are obtained, located remotely via a network by a computing device, that correspond to a font associated with a request to output text using the font. A layout and glyph dependencies of the text is generated by the computing device using the obtained one or more layout tables to identify glyphs that are involved in an output of the text. The identified glyphs are obtained by the computing device from a font file located remotely from the computing device via the network and the text is rendered by the computing device using the obtained glyphs.
US09940736B2
According to one embodiment, a medical image diagnostic apparatus includes a storage memory, processing circuitry, and a display. The storage memory stores data of a plurality of FFR distribution maps constituting a time series regarding a coronary artery, and data of a plurality of morphological images corresponding to the time series. The processing circuitry converts the plurality of FFR distribution maps into a plurality of corresponding color maps, respectively. The display displays a plurality of superposed images obtained by superposing the plurality of color maps and the plurality of morphological images respectively corresponding in phase to the plurality of color maps. The display restricts display targets for the plurality of color maps based on the plurality of FFR distribution maps or the plurality of morphological images.
US09940735B2
The present invention provides a system and method for generating a CT slice image. The system comprises an MIP image generation module, a region of interest determination module, an angle setting module, a curve determination module, a match module and a slice generation module. The MIP image generation module generates MIP images of a reconstructed image; the region of interest determination module determines an image range in an original slice, and determines the parts of the MIP images within the image range as regions of interest; the angle setting module rotates the regions of interest to a plurality of specific angles for a plurality of times; the curve determination module generates a plurality of two-dimensional projected curves of the regions of interest for the plurality of specific angles; the match module selects a two-dimensional projected curve matching with a part to be diagnosed based on features of the plurality of two-dimensional projected curves; the slice generation module determines a slice position range and a slice angle based on the features of the matched curve and the corresponding specific angle.
US09940731B2
Asymmetries are detected in one or more images by partitioning each image to create a set of patches. Salient patches are identified, and an independent displacement for each patch is identified. The techniques used to identify the salient patches and the displacement for each patch are combined in a function to generate a score for each patch. The scores can be used to identify possible asymmetries.
US09940727B2
The present disclosure describes systems and techniques relating to generating three dimensional (3D) models from range sensor data. According to an aspect, frames of range scan data captured using one or more three dimensional (3D) sensors are obtained, where the frames correspond to different views of an object or scene; point clouds for the frames are registered with each other by maximizing coherence of projected occluding boundaries of the object or scene within the frames using an optimization algorithm with a cost function that computes pairwise or global contour correspondences; and the registered point clouds are provided for use in 3D modeling of the object or scene. Further, the cost function, which maximizing contour coherence, can be used with more than two point clouds for more than two frames at a time in a global optimization framework.
US09940723B2
In part, the disclosure relates to method for identifying regions of interest in a blood vessel. The method includes the steps of: providing OCT image data of the blood vessel; applying a plurality of different edge detection filters to the OCT image data to generate a filter response for each edge detection filter; identifying in each edge detection filter response any response maxima; combining the response maxima for each edge detection filter response while maintaining the spatial relationship of the response maxima, to thereby create edge filtered OCT data; and analyzing the edge filtered OCT data to identify a region of interest, the region of interest defined as a local cluster of response maxima. In one embodiment, one or more indicia are positioned in one or more panels to emphasize a reference vessel profile as part of a user interface.
US09940712B2
Methods and systems are provided for the automated detection and analysis of structural tissue alterations related to myelin and axons/neurons in one or more biological structures of a patient's nervous system obtained from data from a medical imaging system, or the initial sensing or data collection processes such as, those that could be used to generate an image. In some embodiments, the method comprises, at a system having a memory and one or more processor for processing and displaying images of the biological structure, computationally processing at least a T1 weighted magnetic resonance image of the structure and a T2 weighted magnetic resonance image of the structure in order to analyze at least a portion of the structure of the nervous system using a plurality of stored tissue classifier elements to determine if the portion of the structure correlates with the presence of myelin. Such methods are useful for the detection of diseases associated with demyelination.
US09940706B2
An image processing apparatus which extracts a lesion having a ground glass opacity from an image includes a change unit which changes a pixel value corresponding to a candidate region for the ground glass opacity to a predetermined pixel value range, a first feature amount extraction unit which obtains a first feature amount from the image, the pixel value of which is changed, and an extraction unit which extracts the lesion from the image based on the first feature amount.
US09940696B2
A display assembly includes a display console displaying at least one image on an image plane. The image is divided into a plurality of pixels. A controller is operatively connected to the display console and includes a processor and tangible, non-transitory memory on which is recorded instructions for executing a method for dynamically adjusting the image in real-time for off-axis viewing. The controller is programmed to generate a compensation-over-viewing-angle map which includes respective compensation factors for each of the plurality of pixels for multiple viewing positions. In one embodiment, the controller is programmed to apply separate respective compensation factors for the instantaneous viewing positions of a first user at a time j and a second user at a time k. In another embodiment, the controller is programmed to apply first and second compensation factors simultaneously at a time m, for a first image and a second image, respectively.
US09940685B2
The present disclosure relates to digital watermarking. One claim recites a method to detect two or more different digital watermarks in media. The method includes: receiving captured imagery of the media, the captured imagery comprising a plurality of image frames; for a first image frame applying a first watermark detector to search for a first digital watermark hidden within the first image frame, in which an electronic processor is programmed as the first watermark detector; and for a second image frame applying a second, different watermark detector to search for a second, different watermark hidden within the second image frame, in which an electronic processor is programmed as the second watermark detector. Other claims and combinations are provided too.
US09940684B2
The disclosure relates to image signal processing, encoded signals and fingerprinting. Lighting information, associated with image capture, is used to adapt a signal encoder to fingerprint generator. The encoder or generator can be adapted by applying different weightings to different color channels, the different weightings being associated with the lighting information.
US09940679B2
Systems, methods, and computer-readable media are provided for verifying parameters for a user-created event. In accordance with one implementation, a computer-implemented method is provided that comprises receiving a set of parameters for an event created by a user. Further, the method includes verifying the set of parameters for the event by comparing the set of parameters to source data and determining, based on a result of the verification, replacement data for one or more of the set of parameters for the event. The method also includes presenting, on a display device, the replacement data for selection by the user and updating, based on a selection received from the user, the set of parameters for the event to include the replacement data.
US09940676B1
System and methods are disclosed for determining properties of vehicle insurance policies for vehicles that engage in autonomous driving. Vehicle driving data, an autonomous driving system quality rating, and/or other information may be used to determine, for example, a premium, a deductible, a coverage term, and/or a coverage amount of an automobile insurance policy of an automobile that engages in autonomous driving. In addition, vehicle driving data and/or other information may be used to determine a distance-based autonomous driving insurance factor based at least in part on a distance traveled by the vehicle while the vehicle was engaged in autonomous driving.
US09940673B2
The systems and methods described herein can identify meaningful relationships between variables, such as particular investments or general asset classes. Unlike conventional correlation analysis, these systems and methods provide an improved technique of comovement analysis that implements a threshold to eliminate data “noise” and then discretizes the remaining observations to normalize any outliers. Such comovement analysis has numerous advantages over known techniques for characterizing relationships between variables. In some embodiments, this improved comovement analysis can be used to calculate a covariance matrix for purposes of mean-variance optimized portfolio construction.
US09940663B2
An Indoor location mapping and wayfinding system for mapping waypoints on an interactive mapping system that can function both indoors and outdoors based on user selections and location. It can include a shopping system that allows users to pre-select items for purchase, maps the items on an indoor map of the store, and provides a route to the user for the collection of the selected items.
US09940659B1
Techniques for determining and providing a preferred layout of a network page may be provided. For example, the system may receive a query with a keyword, access data regarding previous users' interactions associated with the results of the keyword, determine a category associated with the interactions, and provide a display (e.g., on the original network page) for that particular category. In some examples, the system may provide generic network pages and item- or category-specific network pages associated with a particular layout or presentation characteristics. The system can identify the presentation characteristics of the category-specific network page and incorporate them with the generic network page, without redirecting the user to the category-specific network page.
US09940651B2
A transport arrangement system operates to receive a transport request from a user, and to make a selection of a vehicle type for the user based at least in part on a set of criteria associated with the transport request or user information. For example, the determination of whether an autonomous vehicle is to be provided can be based at least in part on the destination specified with the transport request.
US09940647B2
A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU. The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream.
US09940636B2
Embodiments of the invention are directed to systems, methods and computer program products for reverse couponing. An exemplary apparatus is configured to determine user information and account information associated with a user; adjust offer information associated with an offer based on the user information and the account information, wherein the offer enables the user to receive at least one of a discount or a rebate on a purchase from a merchant; and transmit the adjusted offer to the user.
US09940633B2
A system and method for detection of drive-arounds in a retail setting. An embodiment includes acquiring images of a retail establishment, analyzing the images to detect entry of a customer onto the premises of the retail establishment, tracking a detected customer's location as the customer traverses the premises of the retail establishment, analyzing the images to detect exit of the detected customer from the premises of the retail establishment, and generating a drive-around notification if the customer does not enter a prescribed area or remain on the premises of the retail location for at least a prescribed minimum period of time.
US09940628B2
Various systems and methods for measuring ad impression effectiveness are provided. A method is provided comprising selecting, by an ad impression processor, a target consumer for an ad impression, delivering the ad impression to the target consumer, determining, by the processor, a behavior of the target consumer after a time period elapses, wherein the determining comprises analyzing internal data relating to the target consumer.
US09940626B2
Methods and apparatus to provide an electronic agent are disclosed. An example method includes receiving an interactive program via a network at a first information presenting device, accessing a list of keywords associated with the interactive program via the network, accessing a first database using at least one of the keywords, and presenting an electronic agent on the first information presenting device to at least one of present information retrieved from the first database or offer to retrieve information identified via the first database.
US09940612B1
A payment reader and a POS terminal may communicate over a wireless connection. The methods and systems include receiving, from POS terminal, a request for establishing a network connection with the payment card reader. The server determines whether the payment card reader is associated with the POS terminal or a payment application thereon. If the payment card reader is not associated with the POS terminal or the payment application thereon, the server determines the probability of the request being fraudulent.
US09940607B2
A system and method for recording electronic attendance, comprising the steps of: establishing, by a mobile device, a communication link between a server and the mobile device; activating, an application of the mobile device via an verification process; upon activation of the application, detecting and identifying, by the application, a checkpoint station carrying information relating to a checkpoint identifier; establishing, by the mobile device, a communication link between the checkpoint station and the mobile device for data transmission; reading, by the application, information relating to the checkpoint identifier from the checkpoint station; generating, by the application, an encrypted attendance record; transmitting, by the application, the encrypted attendance record to the server via the communication network; decrypting, by a decoder of the server, the encrypted attendance record; and updating, by the server, the record to an attendance report of an account.
US09940606B2
Employers or recruiters populate an online database with job postings. The concepts that job applicants need to have learned to be successful applicants for a job are stated or inferred from the job posting and optionally resumes of others who have held that job. A student's own learning activities are logged by an online education platform. From a comparison between the student's completed learning units and a job posting's required learning units, a personalized learning unit gap can be identified for a student. The online education platform can then recommend how the student can fill the gap by undertaking the study of learning units on the education platform.
US09940605B2
In one embodiment, a server providing an on-line service identifies a change associated with a mobile computing device of a user of the on-line service, the on-line service being accessible to the user through a website hosted by the system; the server also in response to the change and without manual user input from the user, modifies aspects of web pages of the website that are associated with use of the on-line service by the user.