US09577715B2
A resonance system that receives power from a power source section is configured by at least a primary resonance coil, a secondary resonance coil, and a load. The output frequency fo of the power source section is set to lie within one of the frequency ranges f1≦fn≦f2, f3≦fo≦f4, . . . , f2n-1≦fo≦f2n. The frequencies f1, f2, f3, f4, . . . , f2n-1, f2n (f1
US09577712B2
A non-display signal encoding method cooperates with a matrix substrate including a plurality of electrodes. The electrodes cross each other and transmit a plurality of display signals and a plurality of non-display signals. The non-display signal encoding method comprises steps of: transmitting the non-display signals by at least one of the electrodes during a first time; and receiving by coupling at least a part of the non-display signals by at least an external object, wherein the non-display signals have at least three states, i.e. a first state, a second state, a third state or their any combination, and the first, second and third states are different from one another. A matrix substrate is also disclosed.
US09577706B2
Disclosed is a method and apparatus for reducing outbound interference in a broadband powerline communication system. Data is modulated on first and second carrier frequencies and is transmitted via respective first and second lines of the powerline system. A characteristic of at least one of the carrier signals (e.g., phase or amplitude) is adjusted in order to improve the electrical balance of the lines of the transmission system. This improvement in electrical balance reduces the radiated interference of the powerline system. Also disclosed is the use of a line balancing element on or more lines of the powerline system for altering the characteristics of at least one of the power lines in order to compensate for a known imbalance of the transmission system.
US09577703B2
In one embodiment, a method for blindly detecting low density activity includes receiving, by a first node from a second node, a signal and executing a joint message passing algorithm (JMPA) on the signal, where executing the JMPA includes jointly producing a decoded signal and an activity list in accordance with the decoded signal, and calculating a plurality of a priori probabilities in accordance with a plurality of log likelihood ratios (LLRs) corresponding to the signal and a plurality of decoded LLRs.
US09577700B2
An intelligent backhaul radio that has an advanced antenna system for use in PTP or PMP topologies. The antenna system provides a significant diversity benefit. Antenna configurations are disclosed that provide for increased transmitter to receiver isolation, adaptive polarization and MIMO transmission equalization. Adaptive optimization of transmission parameters based upon side information provided in the form of metric feedback from a far end receiver utilizing the antenna system is also disclosed.
US09577692B2
An electronic device and method of managing a Subscriber Identification Module (SIM) are provided. The electronic device includes a memory configured to store at least one instruction; and a provisioning manager connected to the memory, wherein the instruction related to an operation performance of the provisioning manager is configured to search for an accessible communication service provider network on the basis of a Subscriber Identification Module (SIM) where a profile relating to a communication service connection of at least one communication service provider network is not installed and collect at least one communication service provider information on the basis of the found communication service provider network.
US09577691B2
A front end circuit includes a switch including a common terminal and a plurality of individual terminals, in which at least two kinds of reception signals of different frequency bands are input to the common terminal, and in which one of the at least two kinds of reception signals is output to an individual terminal selected from the plurality of individual terminals, and in which a non-selected terminal is grounded, and a balun including a first terminal and a second terminal defining unbalanced ports as well as a third terminal and a fourth terminal defining balanced ports. The first individual terminal of the switch is indirectly connected to the first terminal of the balun and the second individual terminal of the switch is indirectly connected to the second terminal of the balun. The at least two kinds of reception signals are output in a balanced mode from the third terminal and the fourth terminal of the balun.
US09577689B2
Apparatus and methods for analog-to-digital conversion of quadrature receive signals are provided herein. In certain implementations, a transceiver system includes at least a first pair of analog-to-digital converters (ADCs) associated with a first quadrature receiver channel and a second pair of ADCs associated with a second quadrature receiver channel. The first and second pairs of ADCs can provide analog-to-digital conversion of the same receive signal, but can have different noise profiles relative to one another, such as a low pass noise profile and a band pass noise profile. The transceiver system can further include a reconstruction filter for combining the outputs of at least the first and second pairs of ADCs to generate output signals associated with a lower overall noise profile relative to that of either pair of ADCs alone.
US09577684B1
Described herein are technologies related to an implementation of a time interleaved digital-to-time converter (DTC) topology to generate high frequency phase modulated local oscillator (LO) signals. A first and second DTC are connected to an oscillator where outputs of the two DTCs are combined to generate a phase modulated signal and the two DTCs have a frequency rate that is half the frequency rate of the phase modulated signal. The two DTCs can operate at a 50 percent or lower duty cycle.
US09577674B2
A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
US09577668B2
Apparatuses, systems, and computer program products that encode and/or decode information of a video stream, such as an MPEG-4 video stream, are disclosed. Some embodiments comprise an apparatus having a binarizer module to create a plurality of bins for a syntax element for information of the video stream, a context selection module to generate an index value and a most probable symbol (MPS) value for encoding the plurality of bins, and an arithmetic coding module to encode a first and a second bin of the plurality of bins based on a first probability value and a second probability value, respectively, wherein the first and second probability values are determined via the generated index value and MPS value. Examples of some embodiments are high definition personal video recorders, transcoders, computers, personal digital assistants, cellular telephones, portable video players, high definition digital versatile disc (HD-DVD) devices, and Blu-ray disc-read only memory (BD-ROM) devices.
US09577656B2
A method, including receiving an input analog signal containing noise at a specific noise frequency and digitizing the input analog signal to form a digitized signal. The method also includes recovering a first amplitude and a first phase of the noise from the digitized signal, and generating an analog correction signal at the specific noise frequency. The analog correction signal has a second amplitude equal to the first amplitude and a second phase opposite to the first phase. The method further includes summing the input analog signal with the analog correction signal to generate an output analog signal.
US09577653B2
Techniques, systems, and devices are disclosed for implementing a quasi-linear spin-torque nano-oscillator based on exertion of a spin-transfer torque on the local magnetic moments in the magnetic layer and precession of the magnetic moments in the magnetic layer within a spin valve. Examples of spin-torque nano-oscillators (STNOs) are disclosed to use spin polarized currents to excite nano magnets that undergo persistent oscillations at RF or microwave frequencies. The spin currents are applied in a non-uniform manner to both excite the nano magnets into oscillations and generate dynamic damping at large amplitude as a feedback to reduce the nonlinearity associated with mixing amplitude and phase fluctuations.
US09577651B2
A circuit to generate a sweep frequency signal that includes a reference frequency source to generate a reference frequency signal, a first frequency combination circuit coupled to the reference frequency source, and operative to generate a sweep frequency signal in a first frequency band based on the reference frequency signal, a second frequency combination circuit coupled to the reference frequency source, and operative to generate a sweep frequency signal in a second frequency band different from the first frequency band based on the reference frequency signal, a multiple-level switch coupled to outputs of the first frequency combination circuit and the second frequency combination circuit, and a control circuit controlling the first and second frequency combination circuits and the multiple-level switch to output the sweep frequency signal in the first frequency band and the sweep frequency signal in the second frequency band at an output of the multiple-level switch alternately.
US09577648B2
A clock synchronization circuit has a clock sync detector. A first variable delay circuit is coupled to a first input of the clock sync detector. A controller is coupled to a digital output of the clock sync detector and a control input of the first variable delay circuit. A first clock signal is coupled to the first variable delay circuit. A second clock signal is coupled to a second input of the clock sync detector. The clock sync detector includes a first flip-flop and a first delay element coupled between the first variable delay circuit and a data input of the first flip-flop. A second variable delay circuit is coupled to a second input of the clock sync detector. A multiplexer is coupled between the first variable delay circuit and the first input of the clock sync detector. An offset compensation calibrates the clock sync detector.
US09577632B2
A wireless switching circuit includes a charging capacitor, a voltage converter, an infrared sensor unit, a single chip microcomputer (SCM), a zero trigger circuit, and a thyristor. The charging capacitor is used to store and supply power. The voltage converter is used to convert alternating current (AC) voltage into direct current (DC) voltage to charge the charging capacitor. The infrared sensor unit is used to output control signals according to sensed infrared signals. The SCM outputs a trigger signal according to the control signals from the infrared sensor unit. Input ends of the zero trigger circuit are connected to the SCM to receive the trigger signal. An anode and a cathode of the thyristor is connected to a power supply line for the socket. A control end of the thyristor is connected to an output end of the zero trigger circuit.
US09577630B2
An electronic device that includes a power on reset, a variable power supply filter coupled to the power on reset, and control logic coupled to the power on reset and the variable power supply filter. The control logic is configured to activate the variable power supply filter based on a core domain of the electronic device being active.
US09577625B2
A semiconductor device including a common delay circuit configured to delay an input signal in response to a delay control code to output a first delayed input signal and a second delayed input signal; a first delay circuit configured to delay the first delayed input signal in response to the delay control code and to output a first output signal; and a second delay circuit configured to delay the second delayed input signal in response to the delay control code and to output a second output signal.
US09577624B2
A power supply apparatus including: a boost converter configured to generate a power supply voltage to drive to a load circuit from a voltage received from a voltage generation unit; an oscillator configured to receive the minute voltage, and to generate an alternating current signal; and a signal conversion circuit which further includes a half-wave generation circuit configured to receive the alternating current signal, and to generate a half-wave signal of a high potential side or a low potential side, and at least one inverter configured to receive the generated half-wave signal, and to generate a pulse signal; wherein the boost converter is driven by the pulse signal output from the signal conversion circuit in order to generate the power supply voltage.
US09577619B2
Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output buffer circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals.
US09577617B2
The present invention provides a level conversion circuit. The circuit is as follows: A cathode of a first equivalent diode is connected to a reference voltage, and an anode of the first equivalent diode is separately connected to a gate of a first switching transistor and a first end of a first capacitor; a second end of the first switching transistor and a first end of a second switching transistor are connected together; a second end of the second capacitor is separately connected to a cathode of a second equivalent diode and a gate of the second switching transistor; and a second end of the second switching transistor is grounded, and an anode of the second equivalent diode is connected to a reference voltage.
US09577606B2
A duplexer includes an antenna terminal, a transmission amplifier terminal and a reception amplifier terminal. The transmission amplifier terminal is coupled to the antenna terminal via a transmission filter. The reception amplifier terminal is coupled to a reception filter and the reception filter is coupled to the antenna terminal via a band-stop filter.
US09577593B2
Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side of the CMOS input structure of the 2nd and 3rd stages of the op-amp, while the main signal path is through the N-side. According to some embodiments, to balance the relative strengths of the main path and feed-forward paths, the 2nd-stage NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.
US09577592B2
There is disclosed a method for controlling a power amplifier capable of utilizing nonlinearity correction in a nearly steady operation status of non-linearity correction, in a periodical fast switching system in time domain. The method may comprise receiving a periodic switch signal indicating switch time of the periodical fast switching system; and providing, based on the periodic switch signal, a pre-bias signal with a pre-determined voltage amplitude to the power amplifier for a pre-determined time period before each downlink time slot to preheat a transistor of the power amplifier so as to compensate a temperature change of a die inside the transistor.
US09577590B2
A direct current (DC)-DC converter, which includes a charge pump buck power supply and a buck power supply is disclosed. The charge pump buck power supply includes a charge pump buck converter, a first inductive element, and an energy storage element. The charge pump buck converter and the first inductive element are coupled in series between a DC power supply, such as a battery, and the energy storage element. The buck power supply includes a buck converter, a second inductive element, and the energy storage element. The buck converter and the second inductive element are coupled in series between the DC power supply and the energy storage element. As such, the charge pump buck power supply and the buck power supply share the energy storage element.
US09577583B2
A power amplifier may include a first amplifying unit receiving a first bias signal to amplify a power level of an input signal; an envelope detecting unit detecting an envelope of the input signal; a comparing circuit unit comparing a peak value of the detected envelope with a preset reference voltage; and a second amplifying unit amplifying the power level of the input signal according to a second bias signal set depending on a comparison result of the comparing circuit unit.
US09577579B2
A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.
US09577562B2
A method includes driving a component in an electromagnetic actuator back and forth during one or more cycles of the actuator, where the actuator includes a voice coil. The method also includes identifying a back electromotive force (EMF) voltage of the voice coil during at least one of the one or more cycles. The method further includes determining whether a stroke of the component is substantially centered using the back EMF voltage of the voice coil. In addition, the method includes, based on the determination, adjusting one or more drive signals for the voice coil during one or more additional cycles of the actuator. Determining whether the stroke of the component is centered could include determining whether the back EMF voltage of the voice coil is substantially maximized or determining whether times between extremes in the back EMF voltage are substantially equal.
US09577560B2
A synchronous machine control device is provided with a magnet state outputter that estimates a magnetic flux of a permanent magnet forming the magnetic field of a synchronous machine. In a magnet state correction value calculation mode, the magnet state outputter calculates a magnet state correction value. In a magnet state estimation mode, the magnet state outputter obtains, from a magnet state estimation device, a magnetic flux estimation value of the permanent magnet under a given condition of a magnetic flux command and a δ-axis current command and controls a magnet state corrector to correct the magnetic flux estimation value of the permanent magnet obtained by the magnet state estimation device, by use of the magnet state correction value.
US09577552B2
A motor controller for an electric motor having a stator and a rotor. The motor controller includes a power input for receiving AC power from a power source; a control input for receiving a control signal from a control; and circuitry for switching power from the power source to the electric motor in response to the control signal. The circuitry is operable to: apply a braking waveform to the stator while the rotor is rotating; monitor a reactive power of the stator; detect an increase in the reactive power of the stator to determine the rotor has substantially stopped rotating; and remove the braking waveform from the stator in response to detecting the increase in the reactive power.
US09577545B2
A power circuit, a converter structure and a wind power generation system thereof are disclosed. The power circuit includes a first converter having an AC input side and a DC output side, a second converter having a DC input side and an AC output side, and a DC bus storage unit electrically connected to the DC output side of the first converter and the DC input side of the second converter. A level number, a switching valve type and/or a circuit connection of the first converter are different from those of the second converter.
US09577544B2
A device for connecting an electric power generator to an HVDC transmission system is provided, the device having (a) a first unit for converting an AC output voltage from the electric power generator to a DC input voltage for the HVDC transmission system, the first unit having a transformer and a full-bridge rectifier, and (b) a second unit for generating control voltages and/or control currents in the transformer and/or in the electric power generator, the second unit having a PWM full-bridge converter adapted to receive the AC output voltage from the electric power generator or an AC voltage based on said AC output voltage. Furthermore, a system and a method are provided.
US09577534B2
Malfunctions of a switching device included in a power factor corrector are reduced when an instantaneous voltage drop or an instantaneous power failure occurs. If the instantaneous voltage drop or the instantaneous power failure occurs in an AC power source while the power factor corrector is performing a power factor correction operation by boosting an input voltage, an instantaneous power failure controller turns off the switching device included in the power factor corrector so that the power factor correction operation stops. When the commercial power source recovers, too, the power factor corrector suspends the power factor correction operation.
US09577532B2
A switching regulator circuit can include multiple switching regulator stages coupled to an output. A first switching regulator stage may be operated at a different frequency than a second switching regulator stage. In some cases, one switching regulator stage is operated at a different duty cycle. The switching regulator circuit may also include multiple switching regulator stages that cancel ripple at an output node.
US09577528B2
A power converting circuit includes a converter. The converter receives and converts an input power to provide power for a load. The converter includes a power storage unit, a switch unit, a capacitor unit, and a current sampling unit. The power storage unit includes input and output terminals. The switch unit includes first and second switches, which are series connected at a common terminal, and the common terminal is coupled to the output terminal of the power storage unit. The capacitor unit includes first and second capacitors. The first capacitor and the switch unit are parallel connected to form a capacitor-switch parallel structure. The second capacitor capacitance is more than ten times larger than the first capacitor capacitance. The current sampling unit and the capacitor-switch parallel structure are series connected to form a capacitor-sampling unit series structure. The capacitor-sampling unit series structure and the second capacitor are parallel connected.
US09577526B2
A voltage adjusting apparatus includes a pulse width modulation (PWM) controller, a switch module, and a feedback module. The PWM controller outputs control signals. The switch module receives the control signals, and outputs working voltages accordingly. The feedback module includes a jumper, a first resistor, a second resistor, and a third resistor. If the first terminal and the second terminal of the jumper are electrically coupled together, the third resistor is cut off from the feedback module by the jumper, the first resistor and the second resistor are electrically coupled in the feedback module, and the switch module outputs a first working voltage accordingly. If the second terminal and the third terminal of the jumper are electrically coupled together, the first resistor, the second resistor, and the third resistor are all electrically coupled in the feedback module, the switch module outputs a second working voltage accordingly.
US09577521B2
A circuit for controlling a switch in a power converter in which peak current is regulated to achieve a specified average current through a load. Control logic is operable to monitor a voltage across a sensing resistor such that when the voltage across the sensing resistor reaches or exceeds a threshold value, the control logic generates a signal that causes a switch to be turned OFF.
US09577514B2
A peak sample circuit for AC voltage, including: a rectifier coupled to receive an AC voltage and to rectify the AC voltage to generate a rectified signal; a delay circuit coupled to receive the rectified signal and to delay the rectified signal to generate a delayed rectified signal; a comparison circuit coupled to receive the delayed rectified signal and to generate a square signal based on the comparison of the rectified signal and the delayed rectified signal; and a sample output circuit coupled to receive the rectified signal, wherein the sample output circuit samples the rectified signal under the control of the square signal and provides a peak sample signal representative of the peak value of the AC voltage.
US09577510B2
An inverter device includes an inverter circuit, which has switching elements in a bridge connection, a capacitor, which is connected in parallel to the input side of the inverter circuit, a control device, which controls the inverter circuit, a temperature detector, which detects the temperature of the capacitor, a degree-of-deterioration determiner, which determines the degree of deterioration of the capacitor, and a warm-up controller. When the temperature of the capacitor detected by the temperature detector is lower than a prescribed temperature, the warm-up controller controls the switching elements of the inverter circuit to supply a direct current set based on the degree of deterioration and the temperature of the capacitor to the coil of an electric motor connected to the output side of the inverter circuit.
US09577507B2
Disclosed is an inverter assembly without galvanic isolation, the inverter assembly including a PCB mounted with a power supply circuit unit, an inverter unit, an analogue circuit unit and a controller, a first ground circuit pattern to supply a ground power to the power supply circuit unit and the inverter unit, a second ground circuit pattern to supply the ground power to the analogue circuit unit, a third ground circuit pattern to supply the ground power to the controller, a first bead between the first ground circuit pattern and the second ground circuit pattern to isolate an impedance between the first ground circuit pattern and the second ground circuit pattern, and a second bead between the second ground circuit pattern and the third ground circuit pattern to isolate an impedance between the second ground circuit pattern and the third ground circuit pattern.
US09577500B2
A rotary magnetic motor having a rotor configured to magnetically interact with a stator to obtain rotation of the rotor about its axis. The stator has a magnetic structure of a generally involute shape around the axis of rotation. The stator magnetic structure has a plurality of permanent magnets defining a first magnetic face of a first polarity. The rotor has a magnetic structure of a generally circular shape around the axis and inside the stator magnetic structure. The rotor has a plurality of permanent magnets defining a second magnetic face of a second polarity. The magnetic attraction and repulsing of the aligned magnetic faces with a progressively narrowing radial gap, resulting from the involute shape, rotate the rotor inside the stator. A magnetic pulse mechanism discharges a magnetic pulse of the first polarity to provide an additional pull to continue the rotation of the rotor through its full cycle.
US09577484B2
A rotary electric machine includes a stator and a rotor. The rotor has at least one permanent magnet arranged in a d-axis magnetic path. The rotor includes a magnetic gap part located between the permanent magnet arranged in the d-axis magnetic path of one pole and an adjacent magnet with a different polarity, such that a d-axis magnetic flux forms a d-axis bypass passing through an area other than the permanent magnet. The d-axis bypass provides a magnetic resistance in a d-axis direction that is set below a magnetic resistance in a q-axis direction that is orthogonal to the d-axis resistance.
US09577479B2
Disclosed herein is a design for flux switching machines with one or more armature windings which can deliver controlled torque, in either selected direction on start up, without the use of a mechanical position sensor. Flux switching machines without sensors can operate equally well in either direction. The invention discloses design features for such machines which improves the torque profile of the motor with angle. In three phase machines this delivers higher torque and lower ripple torque. In single phase flux switching machines the invention allows the rotor to be placed in a position where maximum torque can be delivered in either direction by selection of either positive or negative armature current. Rotor slotting is introduced to create a path of low permeability across a rotor tooth with minimal impact on the normal torque producing flux paths. Asymmetry of stator slots is used to further create a stable rotor position when energized by predominantly field means or armature means. Starting of the rotor from this stable position can be achieved in either direction. The method is suitable for starting permanent magnet flux switching motors. The invention results in low cost single phase motors which can start and run in either direction and three phase flux switching motors with improved performance over the prior art.
US09577476B2
Performing power transfer to a plurality of power receiving devices, a power transmission device allocates one of a plurality of channels to perform wireless power transfer to a power receiving device in response to a power transmission request transmitted from the power receiving device designating one or more of the plurality of the channels having different frequencies. In a case where a power transmission request using the first channel is received from a second power receiving device, the device stops power transfer to the first power receiving device using the first channel, starts power transfer to the first power receiving device using a channel other than the first channel and starts power transfer to the second power receiving device using the first channel.
US09577472B2
Disclosed herein is a power management apparatus including: a power-demand forecasting section configured to forecast a power demand made by an electric-power demander at a future time; a power measurement section configured to acquire a power consumption of the electric-power demander for the time; a demand control section configured to determine a demand for urging the electric-power demander to adjust the amount of electric power consumed by the electric-power demander on the basis of the power demand forecasted by the power-demand forecasting section and the power consumption acquired by the power measurement section; and a demand issuance section configured to issue the demand determined by the demand control section to the electric-power demander.
US09577467B1
A wireless charger for an electronic device. The charger includes a base having a base opening and an interior cavity defined by an upper shell, a lower shell and an inner sidewall extending between the upper and lower shells to define the base opening. An aperture is formed through the inner sidewall between the interior cavity and the base opening and a hinge is connected to the base within the interior cavity and extends through the aperture. The charger further includes a wireless charging assembly that is pivotably attached to the base by the hinge and moveable between a down position in which the wireless charging assembly is disposed within the base opening and an up position in which the wireless charging assembly extends outside the base. The charging assembly has a charging surface and a power transmitting unit disposed adjacent to the charging surface where the power transmitting unit is configured to wirelessly transmit power across the charging surface to a power receiving unit of a portable electronic device.
US09577465B2
A contactless power transmission device includes a switching unit that switches a power transmission line so that a first power is transmitted through the first line when an AC power supply outputs a first AC power and so that a second power is transmitted through a second line when the AC power supply outputs a second AC power. An impedance conversion unit is arranged on the second line that converts an impedance from an output of the AC power supply to a variable load when the second power is transmitted through the second line to approach an impedance from the output of the AC power supply to the variable load when the first power is transmitted through the first line.
US09577464B2
A wireless charging system includes a first winding portion, a second winding portion which is disposed with an interval between the first winding portion and the second winding portion in an axis direction of the first winding portion, and a pair of magnetic members which are disposed so as to sandwich the first winding portion and the second winding portion in the axis direction. In this case, protrusion portions which protrude toward the other magnetic member are provided in one magnetic member. Also, the magnetic member is held so as to be able to move forward and backward toward the other magnetic member. As a result, since the coefficient of magnetic coupling between a transmitting unit and a receiving unit during charging is enhanced, a charging efficiency can be enhanced.
US09577461B2
Charging a first device by a second device. The first device determines a first position of the first device relative to the second device. Based on the charging position, automatically moving, by the first device, into a second position on the second device. The first device comprises a first motor and a second motor. The first motor is capable of moving the first device along a first axis. The second motor is capable of moving the first device along a second axis.
US09577458B2
An electrical storage system includes: an electrical storage device (10) including serially connected electrical storage blocks; a relay (SMR-B, SMR-G) switching a connection state between the electrical storage device and a load; a controller (30, 34) controlling the relay; and a current interruption circuit (60) interrupting energization of the electrical storage device. The current interruption circuit (60) includes an alarm circuit (63) outputting an alarm signal indicating that any one electrical storage block is overcharged or overdischarged by comparing a voltage value of each electrical storage block with a threshold; a latch circuit (64) retaining the alarm signal; and a transistor (68) causing the relay to switch from an on state to an off state upon reception of a latch circuit output signal. The controller determines an energization state of the electrical storage device after executing control for causing the alarm circuit to output the alarm signal by changing the voltage value or the threshold.
US09577457B2
The present invention provides a control device of a secondary battery. The control device of the secondary battery using, as a positive electrode material, a positive electrode active material that shows a difference of an open circuit voltage curve between during charge and discharge, has a judging unit that judges, on the basis of a charge-discharge state of the secondary battery, whether or not calculation of a current SOC of the secondary battery is possible; and a charge controlling unit that, when judged that the calculation of the current SOC of the secondary battery is not possible by the judging unit, charges the secondary battery up to a predetermined fully charged state.
US09577456B2
This technology relates to a battery device, a control method, and an electric vehicle capable of providing a highly secure anti-theft function. A battery outputs DC power through a power line, a reader/writer communicates by outputting a high-frequency signal through the power line to read authentication information of an electronic device when the electronic device is connected to the battery through the power line, a microcomputer stores the read authentication information and controls the battery when first connection to the electronic device is performed, and performs an authentication process of the electronic device based on the read authentication information and the authentication information stored in the first connection and controls the battery according to a result of the authentication process of the electronic device when second or subsequent connection to the electronic device is performed. This technology may be applied to the battery device mounted on a power-assisted bicycle, for example.
US09577452B2
A portable electronic device includes a connector including first and second data pins and a power pin; a battery charging circuit configured to receive a charging current and a power voltage from an external device via the power pin and charge a battery according to the charging current; and a processor configured to make the first and second data pins, which are shorted by the external device, open and obtain an identification code via the first and second data pins from the external device after the first and second data pins are opened, wherein if the identification code matches a specific code, the processor sends a requirement to the external device, and the power voltage and the charging current received by the battery charging circuit are increased by the external device in response to the requirement.
US09577445B2
The present invention extends to methods, systems, devices, and apparatus for replenishing vehicle resources. Vehicles can be aligned with and docked to replenishment devices. In one aspect, a flying vehicle (e.g., an unmanned aerial vehicle (UAV)) is aligned onto electrical recharging contacts. The flying vehicles fuel level or battery charge can be replenished with minimal, if any, human intervention. Vehicle docking (e.g., landing), alignment, and replenishment can be performed automatically. A circular ring or shaped surface of a vehicle can engage with a conical sloping surface of a docking apparatus as a vehicle moves towards and/or into the docking apparatus. The conical sloping surface shape aligns the vehicle with recharge contacts or a refueling probe at the base of the docking apparatus.
US09577444B2
The disclosure relates to a method for state of charge compensation of a battery having a plurality of battery units. The method comprises the steps of calculating a depth of discharge of each battery unit after the battery units have been charged, calculating an available charge of each battery unit before the battery units are charged, calculating a state of charge compensation requirement value on the basis of the calculated depth of discharge and the calculated available charge for each battery unit, and discharging each battery unit on the basis of the calculated state of charge compensation requirement value. The disclosure also relates to a method for charging a battery which has a plurality of battery units. Also specified are a computer program and a battery management system set up to perform the method, and a battery and a motor vehicle having a drive system connected to such a battery.
US09577442B2
Provided are a cell balance device with high cell balance performance and high cell balance speed and requiring no high voltage process, and a battery system including the cell balance devices. The cell balance device includes: three terminals to be connected to secondary batteries; one terminal to be connected to a voltage hold device; three switches provided between the three terminals and the one terminal; and a receiving terminal and a transmitting terminal for a synchronization signal. Alternatively, the cell balance device includes: four terminals to be connected to secondary batteries; two terminals to be connected to a voltage hold device; six switches provided between the four terminals and the two terminals; and a receiving terminal and a transmitting terminal for a synchronization signal. The battery system includes: a plurality of secondary batteries; a plurality of voltage hold devices; a plurality of cell balance devices; and a clock generation circuit.
US09577437B2
The present invention provides methods and apparatus for reducing power consumption. One method includes detecting the presence of an object, identifying whether the object is a valid device and restricting power if it is not a valid device. Another method includes temporarily applying a low amount of power to the primary unit to detect a load, supplying more power to determine if it is a valid secondary device, and restricting power if it is not. An apparatus for reducing power consumption includes two power inputs, where the lower power input powers a sense circuit. A switch selectively decouples the higher power input from the primary subcircuit during detection mode and couples the higher power input to the primary subcircuit during power supply mode.
US09577422B1
A grounding wire fault circuit interrupter for an electrical machine includes a chassis ground wire, a sensor, and a logic circuit. The chassis ground wire is configured to be electronically connected to a structure of the electrical machine such that the structure of the electrical machine is further electrically connected to one or more power lines that provide electrical power to the electrical machine. The sensor is electronically connected to the chassis ground wire. The logic circuit is electronically connected to the sensor. The sensor is configured to detect current leaks within the electrical machine by sensing electrical power on the chassis ground wire, and the logic circuit is configured to interrupt the flow of electrical power to the electrical machine when the sensor detects a current leak.
US09577417B2
A bracket and a cable mounting system which includes a bracket with a center panel or channel and with magnetic pads located on the distal ends of the center panel or channel so that the bracket may be attached to a structure by magnetic attraction. The cable mounting system may also consist of two brackets set a distance apart and a support rail placed in between and coupled to the brackets.
US09577406B2
Various implementations relating to an illumination package including an edge-emitting laser diode (EELD) are disclosed. In one embodiment, an illumination package includes a heat spreader including a base and a stub that extends from the base, an EELD configured to generate illumination light, the EELD being mounted to a side surface of the stub, and a substrate coupled to the base at a location spaced from the EELD, the substrate being electrically connected to the EELD.
US09577403B2
Techniques are presented herein to set power levels for multiple Raman pump wavelengths in a distributed Raman amplification configuration. A first receive power measurement is obtained at a second node with a controlled optical source at a first node turned on and with a plurality of Raman pump lasers at different wavelengths at the second node turned off. A second receive power measurement is obtained at the second node with the controlled optical source at the first node turned on and the plurality of Raman pump lasers turned on to respective reference power levels to inject optical Raman pump power at a corresponding plurality of wavelengths into the optical fiber span. Based on a target Raman gain and a target Raman gain tilt, respective ratios of a total power are obtained, each ratio to be used for a corresponding one of the plurality of Raman pump lasers.
US09577402B2
A variable-wavelength light source is provided with a first laser medium, a first optical resonator constituted of a total reflection mirror and a half-mirror, a second laser medium, a second optical resonator constituted of a total reflection mirror and the half-mirror, a first filter having a pair of first mirrors configured to cause first light and second light to be transmitted and reflected selectively, a second filter having a pair of second mirrors configured to cause the first light and the second light to be transmitted and reflected selectively, a first drive mechanism configured to operate the first mirror and the second mirror in conjunction with each other, and a second drive mechanism configured to operate the second mirror.
US09577390B2
An electronic device includes an accepting connection terminal to which a connection cable can be connected, and a rotation inhibiting member that inhibits the connection cable from rotating an amount equal to or greater than a predetermined amount around the accepting connection terminal in a state where the connection cable is connected to the accepting connection terminal.
US09577388B2
A connector for being attached to a power-supply unit including a switching element and for mating with a mating connector of a wire harness, the connector including a connecting terminal including an end portion connected to an output terminal in a casing of the power-supply unit, a housing fixed to the casing and enclosing at least a portion of the connecting terminal, a current sensor enclosed in the housing so as to detect a magnetic field generated by an electric current flowing through the connecting terminal, and a signal line for transmitting an output signal of the current sensor.
US09577387B2
An electrical connector includes an insulating body, a shielding sheet disposed in the insulating body, and a ground terminal received in the insulating body for mating with a mating connector. The ground terminal is fixed between a plate surface of the shielding sheet and the insulating body. The ground terminal includes a front end, a middle section, and a rear end having a soldering portion. A first contacting portion is disposed at the front end, a second contacting portion is disposed at the middle section, and the first contacting portion and the second contacting portion respectively electrically contact with the shielding sheet.
US09577385B1
An electrical connector used for mating a mating connector includes an insulating body having multiple terminal slots in communication with an insertion space, multiple terminals, an insulating block. Each terminal slot has at least one side wall from which a depressed portion is depressed, the depressed portion is laterally in communication with the terminal slot. Each terminal has a connection portion connected to a contact portion and a soldering portion, a stopping portion protrudes from the connection portion and is located at the depressed portion. The insulating block is insert molded at a back end of the insulating body. A protruding portion protrudes from a front end of the insulating block and enters the depressed portion. The stopping portion is stopped in front of the protruding portion.
US09577382B2
A stopper (67) of a detector (60) is lockable to a lock surface (17) by entering a lock hole (18) of a lock arm (13) from a deflection space 15. A locking protrusion (45) of a second housing (40) locks to the lock surface (17) by entering the lock hole (18) from a side opposite the deflection space (15). Thus, the housings (10, 40) are held together and the stopper (67) pressed by the locking protrusion (45) separates from the lock surface (17) and the detector can move to the detection position. The locking protrusion (45) has a main body (46) wider than the lock surface (17) of a lock projection (16) and lockable to the lock surface (17). A pressing protrusion (47) narrower than the locking main body 46 projects from the locking main body (46) and enters the lock hole (18) to press the stopper (67).
US09577378B2
The connector of the present disclosure is provided with a lever capable of rotating between an unlocked position in which the lever reclines with respect to the insertion direction of a second housing and a locked position in which the lever is upright with respect to the insertion direction of the second housing. The lever is provided with a protruding portion which comes into contact with the edge of an opening in the adjacent first housing before insertion into the second housing has been completed and which causes the lever to approach the locked position.
US09577372B1
A connector may include at least one power conductor configured to supply power to an electronic device; at least one ground conductor to supply a ground to the electronic device; at least one data conductor configured to carry data to or from the electronic device; optionally, one or more connector orientation conductors; a first magnet on a first side of the connector; and a second magnet on a second side of the connector. The connector may be reversible to be magnetically-connectable to a mating connector in a first orientation and in a second orientation that is 180 degrees from the first orientation. The connector may be operative to carry data and power to and/or from the mating connector when connected to the mating connector in the first orientation or in the second orientation.
US09577368B2
An object of the present invention is to provide a method for manufacturing a connector terminal received in a terminal-receiving chamber, passing through a sealing member, and brought into close contact with the sealing member, and a connector, which are the method for manufacturing a connector terminal, and the connector, for improvement in close contact between the sealing member and the connector terminal. Provided is a method for manufacturing a connector terminal received in a terminal-receiving chamber of a housing, passing through a sealing member filled in the terminal-receiving chamber, and brought into close contact with the sealing member, and the method includes a first process of punching a non-plated metal plate to form an intermediate material and a second process of covering the intermediate material with plating.
US09577361B2
In some embodiments, an apparatus includes a land grid array connector positioned above an electrical package. The apparatus also includes a channel housing positioned above the land grid array. The apparatus includes an electrical-to-optical transceiver positioned in an opening of a socket of the channel housing, wherein a tapered opening is formed above the electrical-to-optical transceiver in the channel housing after the electrical-to-optical transceiver is positioned in the opening of the socket of the channel housing. A gap of the tapered opening decreases progressively starting from the opening of the socket. A conductive wedge positioned in the gap of the tapered opening.
US09577357B2
An electrical connector for electrically connecting with a chip module includes an insulating body having a bottom wall, multiple rows of terminals located in the bottom wall for electrically connecting the chip module, and a carrier for carrying the chip module to the insulating body. Two first side walls extend from two opposite sides of the bottom wall upward, and two second side walls extend from the other two opposite sides of the bottom wall upward. There are a first gap between the first side wall and a most peripheral terminal corresponding to the first side wall, and a second gap between the second side wall and a most peripheral terminal corresponding to the second side wall. The first gap is greater than the second gap. The carrier has a buckling portion, received in the first gap, and for buckling a bottom surface of the chip module.
US09577347B2
A turnstile antenna has two dipoles which have a galvanic contact at the crossing point. The dipoles are arranged in a geometrically asymmetrical manner with respect to the crossing point. The turnstile antenna can be arranged either in a free space or over a metal plate.
US09577343B2
A method and apparatus configures a beamforming coefficient based on the signal strength information without collecting channel information by adjusting the phase of the antennas through random perturbation. An antenna control method of a base station in a wireless communication system using a beamforming technique includes measuring nth received signal strength at nth phase of at least one receive antenna, measuring (n+1)th received signal strength at (n+1)th phase shifted randomly from the nth phase in one of forward and backward directions, and configuring a beamforming coefficient with the phase at which the received signal strength is greatest through comparison of received signal strengths. The random perturbation-based beamforming method and apparatus of the present disclosure is capable of configuring the beamforming coefficient appropriate for the normal cellular environment using a plurality analog array antenna without channel estimation overhead.
US09577342B2
A waveguide includes a dielectric substrate having first and second opposed surfaces defining a longitudinal wave propagation path therebetween; and a conductive grid on the first surface of the substrate and comprising a plurality of substantially parallel metal strips, each defining an axis. The grid renders the first surface of the substrate opaque to a longitudinal electromagnetic wave propagating along the longitudinal wave propagation path and polarized in a direction substantially parallel to the axes of the strips. The grid allows the first surface of the substrate to be transparent to a transverse electromagnetic wave having a transverse propagation path that intersects the first and second surfaces of the substrate and having a polarization in a direction substantially normal to the plurality of metal strips. A diffraction grating on the second surface allows the waveguide to function as an antenna element that may be employed in a beam-steering antenna system.
US09577329B2
An antenna including a ground plane, a broadband radiating element mounted on the ground plane and including a feed point, the feed point having a first impedance, a feed for feeding the broadband radiating element at the feed point, the feed having a second impedance and a ground leg extending between the broadband radiating element and the ground plane for impedance matching the first impedance to the second impedance, the ground leg being capacitively coupled to the broadband radiating element.
US09577327B2
Described embodiments include an electromagnetic beam steering apparatus. The apparatus includes a first blazed transmission diffraction grating component configured to angularly deflect an electromagnetic beam at a first blaze angle. The apparatus includes a second blazed transmission diffraction grating component configured to angularly deflect an electromagnetic beam at a second blaze angle. The apparatus includes an electromagnetic beam steering structure configured to independently rotate the first blazed transmission diffraction grating component and the second blazed transmission diffraction grating component about a coaxial axis such that an electromagnetic beam incident on the first blazed transmission diffraction grating component exits the second blazed transmission diffraction grating component as a steered electromagnetic beam.
US09577321B2
An antenna set includes a first antenna, a second antenna, and a neutralized line. Each of the first antenna and the second antenna has a low frequency resonant path and a high frequency resonant path. The neutralized line is couple to the low frequency resonant path of the first antenna and the low frequency resonant path of the second antenna. The low frequency resonant path of the first antenna and the low frequency resonant path of the second antenna correspond to a first frequency band, the high frequency resonant path of the first antenna and the high frequency resonant path of the second antenna correspond to a second frequency band, and the two low frequency resonant paths do not overlap the two high frequency resonant paths.
US09577308B2
An interconnecting structure for electrically connecting a first electronic device with a second electronic device is provided. The first electronic device has two first bond-pads, and the second electronic device has two second bond-pads electrically connected to the two first bond-pads respectively. The interconnecting structure includes a signal transmission structure electrically connected to the two first bond-pads and the two second bond-pads; and a ground device disposed between the first electronic device and the second electronic device so that the first electronic device and the second electronic device have a same ground potential.
US09577307B2
Aspects of the subject disclosure may include, for example, a transmission device that includes a transmitter that generates a first electromagnetic wave to convey data, the first electromagnetic wave having at least one carrier frequency and corresponding wavelength. A coupler couples the first electromagnetic wave to a transmission medium having at least one inner portion surrounded by a dielectric material, the dielectric material having an outer surface and a corresponding circumference, wherein the coupling of the first electromagnetic wave to the transmission medium forms a second electromagnetic wave that is guided to propagate along the outer surface of the dielectric material via at least one guided-wave mode that can include an asymmetric mode, wherein the at least one carrier frequency is within a microwave or millimeter-wave frequency band and wherein the at least one corresponding wavelength is less than the circumference of the transmission medium. Other embodiments are disclosed.
US09577305B2
A stripline RF transmission cable has a flat inner conductor surrounded by a dielectric layer that is surrounded by an outer conductor. The outer conductor has a top section and a bottom section which transition to a pair of edge sections that interconnect the top section with the bottom section. The top section, bottom section and the inner conductor may be provided with generally equal widths. An average dielectric constant of the dielectric layer may be lower between the inner conductor edges and the edge sections than between a mid section of the inner conductor and the top and the bottom sections and/or spacing between the inner conductor and the dielectric layer may be reduced proximate a mid section of the inner conductor.
US09577301B2
A feeding network is realized by dielectric phase shifting module. The module includes a dielectric device into which interlayer space is defined, a first conductor and a second conductor disposed side by side into the interlayer space and a third conductor located outside of the interlayer space and connected, at different locations, to one end, located at a same side, of each of the first and second conductors. Another end of the first conductor is defined as an input end, while another end of the second conductor and any end of the third conductor are all defined as output ends. The dielectric device is configured to slide along a longitudinal direction of the first and second conductors under external force so as to change phase of signals fed in from the input end and fed out from the output ends. Two dielectric phase-shift modules constitute a phase-shift unit thereof.
US09577297B2
An electrochemical cell is presented. The cell includes a housing having an interior surface defining a volume, and an elongated separator disposed in the housing volume. The elongated separator defines an axis of the cell. The separator has an inner surface and an outer surface. The inner surface of the separator defines a first compartment. The outer surface of the separator and the interior surface of the housing define a second compartment having a volume. The cell further includes a conductive matrix disposed in at least a portion of the second compartment volume such that the conductive matrix occupies a gap between the outer surface of the separator and the interior surface of the housing. The gap in the second compartment extends in a direction substantially perpendicular to the axis of the cell.
US09577292B2
An electronic device includes a storing unit which is provided on a battery pack and which retains power information of the battery pack, an acquiring unit which is provided in the main unit and which acquires the power information of the battery pack from the storing unit, and a control unit which is provided in the main unit and which controls the operation of the main unit based on the power information of the battery pack.
US09577291B2
A system and method include receiving a temperature signal from a temperature sensor, controlling operation of an air conditioner condenser, and controlling an electric vehicle charger to operate to charge an electric vehicle battery only when the air conditioner condenser is not running.
US09577279B2
Phosphazenium-based ionomers and methods of making them are disclosed. The ionomers are useful in making membranes for fuel cells and other devices that benefit from extremely base-stable membranes. The polymers (ionomers) contain repeating units of formula: in which all of R1, R2, W, Y and Z are hydrocarbon.
US09577274B2
Provided are an apparatus and a method for managing a fuel cell vehicle system, and more particularly, an apparatus and a method for managing a fuel cell vehicle system capable of optimally maintaining a driving method based on environmental information and product information.
US09577258B2
Provided are a method of preparing a cathode active material, a composite cathode active material, and a cathode and a lithium battery containing the composite cathode active material. The method includes mixing a transition metal source and a reducing agent to prepare a cathode active material precursor; and mixing and calcining the cathode active material precursor to prepare a lithium transition metal oxide, wherein a supplied amount of the reducing agent is about 0.003 mole/hr or less with respect to 1 mole/hr of a supplied amount of the transition metal source.
US09577253B2
A positive-electrode material for a lithium secondary battery which includes a lithium oxide compound or a complex oxide as reactive substance. The material also includes at least one type of carbon material, and optionally a binder. A first type of carbon material is provided as a coating on the reactive substance particles surface. A second type of carbon material is carbon black. And a third type of carbon material is a fibrous carbon material a mixture of at least two types of fibrous carbon material different in fiber diameter and/or fiber length. Also, a method for preparing the material as well as lithium secondary batteries including the material.
US09577250B2
Electrodes having nanostructure and/or utilizing nanoparticles of active materials and having high mass loadings of the active materials can be made to be physically robust and free of cracks and pinholes. The electrodes include nanoparticles having electroactive material, which nanoparticles are aggregated with carbon into larger secondary particles. The secondary particles can be bound with a binder to form the electrode.
US09577247B2
A positive electrode active material capable of improving an output performance of a nonaqueous electrolyte secondary battery is provided. A positive electrode active material of a nonaqueous electrolyte secondary battery 1 contains a first positive electrode active material and a second positive electrode active material. In the first positive electrode active material, the content of cobalt is 15% or more on an atomic percent basis in transition metals. In the second positive electrode active material, the content of cobalt is 5% or less on an atomic percent basis in transition metals. An average secondary particle diameter r1 of the first positive electrode active material is smaller than an average secondary particle diameter r2 of the second positive electrode active material.
US09577246B2
Provided is a negative electrode active material containing SiOx and carbonaceous particles containing graphite and having both good discharge capacity and good electric conductivity. Also provided is a negative electrode using the negative electrode active material and a nonaqueous electrolyte secondary battery. When the carbonaceous particles have an average particle diameter D50 of α (μm) and a BET specific surface area of β (m2/g), the α and the β satisfy the following Formulae (1) and (2). β≦−(12/18)α+12 (1) 5≦α≦15 (2).
US09577245B2
Disclosed is a non-aqueous electrolyte secondary cell excellent in capacity retention rate and I-V characteristics after repeated cycles. The secondary cell contains a negative electrode active material containing scaly graphite particles and coated graphite particles. The coated graphite particles contain graphite particles and a coating layer coating the surfaces of the graphite particles. The coating layer contains amorphous carbon particles and an amorphous carbon layer. It is preferable that the negative electrode active material contain 1 to 6% by mass of the scaly graphite particles and that the graphite particles, the amorphous carbon particles, and the amorphous carbon layer be in a mass ratio of 100:α:β where 1≦α≦10, 1≦β≦10, and α≦1.34β.
US09577241B2
The present invention relates to an apparatus for preventing overcharge of a battery, and more particularly, to an apparatus for preventing overcharge of a battery, which interrupts power of the battery by inducing a fracture of a busbar to prevent overcharge and to this end, provided is an apparatus for preventing overcharge of a battery, including: a battery cell; an electrode tab extended from both sides of the battery cell and constituted by a negative tab and a positive tab; and a busbar connecting the negative tab and the positive tab, wherein the busbar has a cut part fractured by expansion of the battery cell.
US09577239B2
A secondary battery including an electrode assembly. The electrode assembly includes a first electrode including a plurality of first electrode tabs extending to a side of the first electrode, a second electrode including a plurality of second electrode tabs extending to a side of the second electrode, and a separator between the first electrode and the second electrode and insulating the first electrode and the second electrode from one another. The electrode assembly is in a wound jelly roll shape. The plurality of first electrode tabs are in one of four quadrants formed by a long axis and a short axis of the wound electrode assembly. The plurality of second electrode tabs are in a different one of the four quadrants.
US09577236B2
Disclosed is a battery separator, comprising two fiber regions comprising glass fibers, and a middle fiber region disposed between them comprising larger average diameter fibers and specified amounts of silica, or fine fibers, or both; and processes for making the separator. Also disclosed is a battery separator, comprising a fiber region and either one or two silica-containing region(s) adjacent thereto, each of the regions containing a specified amount of silica; and processes for making the separator. Such separators are useful, e.g., in lead-acid batteries.
US09577234B2
The invention relates to a separator material (6) for forming a separator for a lead-acid accumulator, especially in the form of unfinished rolled product, and a method for the production thereof. The inventive separator material (6) comprises a first layer in the form of a microporous film (1) and at least one second layer in the form of a planar fleece material (7). At least one face of the microporous film (1), which is made of a thermoplastic material, is provided with a number of protrusions (2, 2′) defining an area with an increased film thickness on a basic film sheet. The fleece material (7) is welded to the film (1) by means of ultrasonic welding in such a way that the planar fleece material (7) is located at least at the level of the surface of the basic film sheet without invading the same in the area of the welded joints (8).
US09577231B2
A lithium-ion battery module includes a housing having a plurality of partitions configured to define a plurality of compartments within a housing. The battery module also includes a lithium-ion cell element provided in each of the compartments of the housing. The battery module further includes a cover coupled to the housing and configured to route electrolyte into each of the compartments. The cover is also configured to seal the compartments of the housing.
US09577228B2
A battery pack includes a battery side terminal electrically connectible with a device side terminal of a device body that may be a tool body of an electric tool or a charger body of a charger. The battery side terminal includes a first contact portion and a second contact portion. The first contact portion configured to form an electric contact through contact with a first side surface of the device side terminal. The second contact portion configured to form an electric contact through contact with a second side surface opposite to the first side surface of the device side terminal. The first contact portion configured to contact the first side surface in a first contact range having a first length. The second contact portion configured to contact the second side surface in a second contact range having a second length that may be different from the first length.
US09577212B2
A display device includes a substrate, a display unit formed on the substrate, a sealing substrate bonded to the substrate by a bonding layer surrounding the display unit, the sealing substrate comprising a complex member and an insulating member, wherein the complex member has a resin matrix and a plurality of carbon fibers and the insulator is connected to an edge of the complex member and comprises a penetration hole, a metal layer disposed at one side of the sealing substrate wherein the one side faces the substrate, and a conductive connection unit filling in the penetration hole and contacting the metal layer. The complex member and the insulator may be coupled by tongue and groove coupling along a thickness direction of the sealing substrate where the protrusion-groove coupling structure is top-to-bottom symmetric and the insulator may have a thickness identical to that of the complex member.
US09577209B2
The present invention focuses on a structure in which an auxiliary wiring for increasing the conductivity of an upper electrode is provided on the substrate side. The conductive auxiliary wiring of a light-emitting device is provided over a substrate, and an upper portion of the auxiliary wiring protrudes in a direction parallel to the substrate. Further, an EL layer formed in a region including a lower electrode layer and the auxiliary wiring is physically divided by the auxiliary wiring. An upper electrode layer formed in a manner similar to that of the lower electrode layer may be electrically connected to at least part of a side surface of the auxiliary wiring. Such an auxiliary wiring may be used in a lighting device and a display device.
US09577201B2
A compound including a ligand having the formula: is disclosed. In these formulas, each R1, R2, and R3 is independently selected from hydrogen, alkyl, and aryl; at least one of R1 and R2 is a branched alkyl containing at least 4 carbon atoms, where the branching occurs at a position further than the benzylic position; where R1 and R3 are mono-, di-, tri-, tetra-, or no substitutions; and R2 is mono-, di-, or no substitutions. Heteroleptic iridium complexes including such compounds, and devices including such compounds are also disclosed.
US09577197B2
The invention relates to novel polymers containing one or more 3,7-dialkyl-benzo[1,2-b:4,5-b′]dithiophene repeating units, methods for their preparation and monomers used therein, blends, mixtures and formulations containing them, the use of the polymers, blends, mixtures and formulations as semiconductor in organic electronic (OE) devices, especially in organic photovoltaic (OPV) devices, and to OE and OPV devices comprising these polymers, blends, mixtures or formulations.
US09577194B2
A composition comprising: at least one compound comprising a hole transporting core, wherein the core is covalently bonded to a first arylamine group and also covalently bonded to a second arylamine group different from the first, and wherein the compound is covalently bonded to at least one intractability group, wherein the intractability group is covalently bonded to the hole transporting core, the first arylamine group, the second arylamine group, or a combination thereof, and wherein the compound has a molecular weight of about 5,000 g/mole or less. Blended mixtures of arylamine compounds, including fluorene core compounds, can provide good film formation and stability when coated onto hole injection layers. Solution processing of OLEDs is a particularly important application.
US09577188B2
Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.
US09577185B1
An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.
US09577172B2
The present invention relates to a light emitting die component formed by multilayer structures. The light emitting die component comprises a semiconductor structure (103) comprising: an n-type layer (104), an active region (106) and a p-type layer (108); a p-contact layer (110) arranged to be in electrical contact with said p-type layer (108); an n-contact layer (116) arranged to be in electrical contact with said n-type layer (104); a first dielectric layer (114) arranged to electrically isolate said p-contact layer (110) from said n-contact layer (116); a thermal spreading layer (120) comprising a first and a second region (120a, 120b) being electrically isolated from each other, wherein said first region (120a) forming an anode electrode of said light emitting die component and said second region (120b) forming a cathode electrode of said light emitting die component; a second dielectric layer (118) arranged to electrically isolate said n-contact layer (116) from said first region (120a) or to electrically isolate said p-contact layer (110) from said second region (120b); a third dielectric layer (122) arranged to electrically isolate said first and second regions (120a, 120b); and an interconnect pad (124) enabling interconnection with a submount (126).
US09577169B2
Techniques are disclosed for integrating the LED lead frame into the LED circuit fabrication process. The LED packages within the lead frame may be spaced according to the final spacing of the LED packages on the finished circuit board, such that multiple LED packages may be attached to a circuit board at a time by applying the lead frame to circuit board and then removing portions of the lead frame, leaving the LED packages attached to the board. The LED packages may be attached using solder or conductive epoxy, in some embodiments. Alternatively, part of the lead frame may include conductive wires forming one or more strings of LED packages. An entire string of LED packages may then be removed from the lead frame in a single motion and placement may be performed for a string of LED packages all at once rather than for individual LED packages.
US09577165B2
A light emitting diode chip includes a semiconductor layer sequence having an active layer that generates electromagnetic radiation, wherein the light emitting diode chip has a radiation exit area at a front side, the light emitting diode chip has a mirror layer at least in regions at a rear side situated opposite the radiation exit area, said mirror layer containing silver, a protective layer is arranged on the mirror layer, and the protective layer comprises a transparent conductive oxide.
US09577156B2
The present invention provides a Group III nitride semiconductor light-emitting device in which the production method is simplified while migration of at least one of Ag atoms and Al atoms is suppressed, and a production method therefor. The production method comprises steps of forming a first electrode, forming a second electrode, and forming a second electrode side barrier metal layer on the second electrode. Moreover, the second electrode has an electrode layer containing at least one of Ag and Al. In forming the first electrode and the second electrode side barrier metal layer, the second electrode side barrier metal layer is formed on the second electrode while the first electrode to be electrically connected to the first semiconductor layer is formed. The first electrode and the second electrode side barrier metal layer are deposited are deposited in the same layered structure.
US09577142B2
A method to produce a semiconductor laser diode (LD) including a sampled grating (SG) is disclosed. The method prepares various resist patterns each including grating regions and space regions alternately arranged along an optical axis. The grating regions and the space region in respective cavity types have total widths same with the others but the grating regions in respective types has widths different from others. After the formation of the grating patterns based on the resist patterns, only one of the grating patterns is used for subsequent processes.
US09577133B2
Provided are novel Building Integrable Photovoltaic (BIPV) modules having one or more connectors that are movable between extended and retracted positions. Connector adjustment may be performed in the field, for example, during installation of a module. In certain embodiments, a connector includes a connector body and extension body. The extension body flexibly attaches the connector body to the module and allows the connector body to move with respect to the module edge. In an extended position, the connector body is positioned closer to the edge and is configured to make electrical connections to a joiner connector for interconnecting with an adjacent module. In a retracted positioned, the connector body is positioned further from the edge and is configured to make electrical connections to a jumper for interconnecting the conductive elements of the connector. In certain embodiments, a jumper does not protrude beyond the edge when connected to the connector body.
US09577132B2
A solar cell module includes a plurality of solar cells each including a substrate, an emitter region positioned at a back surface of the substrate, first electrodes electrically connected to the emitter region, second electrodes electrically connected to the substrate, a first current collector positioned at ends of the first electrodes, and a second current collector at ends of the second electrodes, and a first connector connecting a first current collector of a first solar cell of the plurality of solar cells to a second current collector of a second solar cell adjacent to the first solar cell. The first current collector of the first solar cell and the second current collector of the second solar cell each have a different polarity.
US09577115B2
A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein.
US09577113B2
A semiconductor device includes a substrate; a gate electrode provided on the substrate; a first insulating layer formed on the gate electrode; an island-shaped oxide semiconductor layer formed on the first insulating layer; a source electrode electrically connected to the oxide semiconductor layer; and a drain electrode electrically connected to the oxide semiconductor layer, wherein the first insulating layer has a recess in the surface, wherein the oxide semiconductor layer is formed on a bottom surface and side walls of said recess and on an upper face of the first insulating layer, and wherein at least one of the source electrode and the drain electrode is disposed on a portion of the oxide semiconductor layer over the side walls of said recess, and is not formed on a portion of the oxide semiconductor layer over the upper face of the first insulating layer.
US09577100B2
A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.
US09577094B2
An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.
US09577090B2
To satisfy both suppression of rise in contact resistance and improvement of breakdown voltage near the end part of a trench part. The trench part GT is provided between a source offset region and a drain offset region at least in plan view in a semiconductor layer, and is provided in a source-drain direction from the source offset region toward the drain offset region in plan view. A gate insulating film GI covers the side surface and the bottom surface of the trench part GT. A gate electrode is provided in the trench part at least in plan view, and contacts the gate insulating film GI. A contact GC contacts the gate electrode GE. The contact GC is disposed, shifted in a first direction perpendicular to the source-drain direction relative to the centerline in the trench part GT extending in the source-drain direction in plan view, and is provided in the trench part GT in plan view.
US09577089B2
First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.
US09577087B2
A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n+-drain region. A peripheral region is provided with a second parallel pn-layer, which has a repetition pitch narrower than the repetition pitch of the first parallel pn-layer. An n−-surface region is formed between the second parallel pn-layer and a first main surface. On the first main surface side of the n−-surface region, a plurality of p-guard ring regions are formed to be separated from each other. A field plate electrode is connected electrically to the outermost p-guard ring region among the p-guard ring regions. A channel stopper electrode is connected electrically to an outermost peripheral p-region of the peripheral region.
US09577079B2
Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.
US09577075B2
A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.
US09577070B2
Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.
US09577068B2
Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors.
US09577067B2
Some embodiments of the present disclosure provide a semiconductor device including a semiconductive substrate, a metal gate including a metallic layer proximal to the semiconductive substrate. A dielectric layer surrounds the metal gate. The dielectric layer includes a first surface facing the semiconductive substrate and a second surface opposite to the first surface. A sidewall spacer surrounds the metallic layer with a greater longitudinal height. The sidewall spacer is disposed between the metallic layer and the dielectric layer. An etch stop layer over the metal gate comprises a surface substantially coplanar with the second surface of the dielectric layer. The etch stop layer has a higher resistance to etchant than the dielectric layer. A portion of the etch stop layer is over the sidewall spacer.
US09577066B1
One illustrative method disclosed herein includes, among other things, forming first and second fins, forming a liner layer above at least a first upper surface of the first fin and a second upper surface of the second fin, and forming an ion-containing region in the first portion of the liner layer while not forming the ion-containing region in second portion of the liner layer. The method also includes performing a liner etching process so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned above the first fin, and performing at least one etching process to define a reduced-height second fin that is less than an initial first height of the first fin.
US09577057B2
Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.
US09577056B2
A semiconductor component having at least one first contact structure for feeding in and/or leading away charge carriers in relation to the semiconductor component, which first contact structure has at least one contact-making point for electrically conductively connecting the first contact structure to an external terminal, and which first contact structure has at least one first-order branching point proceeding from the contact-making point, at which first-order branching point at least one first-order subsequent conduction track branches off. Each first-order subsequent conduction track has at least one second-order branching point, at which second-order branching point at least one second-order subsequent conduction track branches off, and the electrical through-conduction resistance of each second-order subsequent conduction track is higher than the electrical through-conduction resistance of the first-order subsequent conduction track connected to said second-order subsequent conduction track via a common second-order branching point.
US09577055B2
The present disclosure relates to a semiconductor device. Such a semiconductor device includes a trench metal-oxide-semiconductor (MOS) transistor having two or more electrodes in a trench formed on a substrate of the semiconductor, where a part of a shield electrode positioned at a bottom of the trench is formed to have a large thickness, and a groove is formed in a gate electrode that is stacked on the shield electrode, such that a part of the shield electrode protrudes to a surface of the semiconductor device so as to be connected with a source power.In such a manner, by minimizing a region in which the shield electrode and the gate electrode overlap, a region that decreases problematic effects, such as leakage current of gate/source or gate/drain of a trench MOS transistor, and a region where high difference of a gate electrode is generated, are removed.
US09577053B2
The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.
US09577049B1
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a semiconductor layer over the substrate. The semiconductor layer includes a transition metal chalcogenide. The semiconductor device structure includes a source electrode and a drain electrode over and connected to the semiconductor layer and spaced apart from each other by a gap. The source electrode and the drain electrode are made of graphene.
US09577048B1
Heterostructure field-effect transistor (HFET) having a channel layer, a barrier layer disposed on the channel layer, and a gate, source and drain electrodes disposed on the barrier layer, respectively, and corresponding fabrication methods are disclosed. The drain electrode includes a p-type semiconductor patterned structure and a raised drain section, the drain electrode includes a Schottky contact and an ohmic contact, the Schottky contact is formed between a top surface together with a side surface of p-type semiconductor patterned structure and a bottom surface together with a side surface of raised drain section, the ohmic contact is formed between another surface of raised drain section and barrier layer, the raised drain section partially surrounding the p-type semiconductor patterned structure, and a bandgap of the channel layer is less than a bandgap of the barrier layer.
US09577045B2
In a general aspect, a power semiconductor device can include a collector region disposed on a substrate, the collector region can include n-type silicon carbide (SiC). The power semiconductor device can also include a base region disposed on the collector region. The base region can include p-type SiC doped with gallium. The power semiconductor device can include an emitter region disposed on the base region. The emitter region can include n-type SiC carbide.
US09577039B2
A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).
US09577038B1
A method of making a semiconductor device includes forming a nanosheet stack including a first layer and a second layer; patterning a gate stack on the nanosheet stack; forming a first spacer along a sidewall of the gate stack; removing an endwall portion of the nanosheet stack that extends beyond the first spacer such that a portion of the second layer is exposed from a sidewall of the first spacer; depositing a second spacer along a sidewall of the first spacer; recessing the substrate beneath the second spacer to form an isolation region; depositing an oxide on the gate stack and within the isolation region and partially recessing the oxide; removing a portion of the second spacer such that the portion of the second layer is exposed; and growing an epitaxial layer on the portion of the second layer that is exposed to form a source/drain over the isolation region.
US09577036B1
A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.
US09577024B2
An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.
US09577023B2
A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.
US09577019B2
An OLED display and a method of manufacturing the same are disclosed. In one aspect, the display device includes a plurality of pixels, wherein each of the pixels includes a plurality of wires including a first wire extending in a first direction and a second wire extending in a second direction crossing the first direction, the second wire having top and bottom portions opposing each other. The pixels also include a plurality of switching TFTs electrically connected to the wires, a driving TFT configured to supply a driving current, a storage capacitor electrically connected to the wires and the driving TFT, and a connecting wire electrically connecting the driving TFT to a selected one of the switching TFTs, wherein the connecting wire has top and bottom portions opposing each other, and wherein at least the top portions of the connecting wire and the second wire are formed on different layers.
US09577015B2
A method for producing a display device includes forming a resin film on a substrate, forming a plurality of light emitting elements above the resin film, forming a plurality of first grooves in a surface of the resin film, the plurality of first grooves enclosing the plurality of light emitting elements individually in a multiple-fold manner, cutting the substrate at a position overlapping any one of the plurality of first grooves other than the first groove closest to one of the plurality of light emitting elements, and peeling off the substrate from the resin layer.
US09577014B2
A manufacturing method of an organic electroluminescence display device including a device substrate provided with a plurality of pixel electrodes which have a gap part therebetween, a common electrode disposed opposite to the plurality of pixel electrodes, a light emitting layer provided over the plurality of pixel electrodes, and a bank layer provided in the gap part of the plurality of pixel electrodes, the method comprising forming a cover layer including a concave region to fit into a convex shaped part of the bank layer at a support substrate, forming a color filter layer facing the pixel electrode to the concave region, disposing a surface of the color filter layer on the device substrate so that the concave region fits into a convex shaped part, and attaching the cover layer and the color filter layer on the device substrate by peeling the cover layer from the support substrate.
US09577011B2
A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
US09577005B2
There is provided a semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.
US09576998B2
A back-illuminated type solid-state image pickup unit in which a pad wiring line is provided on a light reception surface and which is capable of improving light reception characteristics in a photoelectric conversion section by having a thinner insulating film in a pixel region. The solid-state image pickup unit includes a sensor substrate having a pixel region in which photoelectric conversion sections are formed in an array, and a drive circuit is provided on a surface opposed to a light reception surface for the photoelectric conversion sections of the sensor substrate. A through hole via reaching the drive circuit from the light reception surface of the sensor substrate is provided in a peripheral region located outside the pixel region. A pad wiring line directly laminated on the through hole via is provided on the light reception surface in the peripheral region.
US09576992B2
Light-sensing apparatuses may include a light sensor transistor and a switching transistor in a light-sensing pixel, the transistors being oxide semiconductor transistors. In the light-sensing apparatus, the light sensor transistor and the switching transistor in the light-sensing pixel may be adjacently formed on one substrate, the switching transistor including a channel material that is relatively less light-sensitive than the light sensor transistor and is stable, and the light sensor transistor includes a channel material that is relatively light-sensitive. The light sensor transistor may include a transparent upper electrode on a surface of a channel, and a negative voltage may be applied to the transparent upper electrode, whereby a threshold voltage shift in a negative voltage direction may be prevented or reduced.
US09576991B2
The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer.
US09576987B2
A display substrate includes a substrate having a first region and a second region, a conductive pattern is provided in the first region of the substrate and includes a first conductive pattern and a second conductive pattern, the first conductive pattern has a gate electrode and a source electrode, the second conductive pattern has a source electrode and a drain electrode, an insulation layer pattern is positioned on the conductive pattern and exposes an outer sidewall of the conductive pattern, an organic layer is provided in the first region and the second region of the substrate and covers the insulation layer pattern, and a pixel electrode is provided on the organic layer and is electrically connected to the drain electrode through a contact hole in the organic layer.
US09576979B2
A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.
US09576973B2
Disclosed is a semiconductor device, including: stack structures including interlayer insulating patterns and conductive line patterns, which are alternately stacked, and separated by a first slit; string pillars passing through the stack structures; and dummy holes passing through top portions of the stack structures to be spaced apart from bottom surface of the stack structures and disposed between the string pillars.
US09576971B2
A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
US09576970B2
A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.
US09576969B2
An IC device includes a polycrystalline silicon thin film interposed between a first level semiconductor circuit and a second level semiconductor circuit which are formed on a substrate and disposed to vertically overlap each other. The polycrystalline silicon thin film includes at least one silicon single crystal. The at least one silicon single crystal includes a flat horizontal portion, which provides an active region of the second level semiconductor device, and a pin-shaped protruding portion protruding from the flat horizontal portion toward the first level semiconductor device.
US09576968B2
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
US09576963B2
A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at bottoms of trenches, and each of the embedded word lines is located at a first side wall of one of the trenches and connected to first sides of the semiconductor pillars in the same row. Each of the embedded word lines is not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides. Only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row. An isolation structure is formed between a second side wall of each of the trenches and each of the embedded word lines. The first side wall is opposite to the second side wall.
US09576961B2
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
US09576960B2
According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal.
US09576958B1
An approach to forming a semiconductor structure with improved negative bias temperature instability includes forming an interfacial layer on a semiconductor substrate with an nFET and a pFET. The semiconductor structure includes a gate dielectric layer on the interfacial layer and a pFET work function metal layer on a portion of the gate dielectric layer over an area above the pFET. The semiconductor structure includes a nFET work function metal layer on a portion of the gate dielectric layer over an area above the nFET and on the pFET work function metal layer in the area above the pFET. The semiconductor structure includes a gate electrode metal on the nFET work function metal layer where a plurality of fluorine atoms and a plurality of reducing gas atoms are incorporated into at least a portion of the interfacial layer, the gate layer, and a portion of the nFET work function metal.
US09576954B1
A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.
US09576952B2
Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).
US09576930B2
A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.
US09576929B1
A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.
US09576923B2
Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.
US09576921B2
To improve an integration degree of a semiconductor device.The semiconductor device includes a plurality of wiring layers formed on the semiconductor substrate, a pad electrode formed on an uppermost wiring layer among the plurality of wiring layers, a base insulating film having a pad opening above the pad electrode, and a rewiring electrically connected to the pad electrode and extending over the base insulating film. Further, the semiconductor device includes a protective film covering an upper surface of the rewiring and having an external pad opening exposing part of the upper surface of the rewiring, an external pad electrode electrically connected to the rewiring through the external pad opening and extending over the protective film, and a wire connected to the external pad electrode. Part of the external pad electrode is located in a region outside the rewiring.
US09576918B2
Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a plurality of conductive connection pads are formed on a semiconductor substrate to connect to circuitry formed on the substrate. A post is formed on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is formed over the semiconductor substrate including over the connection pads and the posts. Holes are formed by removing the dielectric layer directly over the posts. The formed holes are filled with a conductive material and a connector is formed over each filled hole.
US09576915B2
Consistent with an example embodiment, a System on Chip (SoC) device operates in millimeter wave frequencies. The SoC device comprises, a silicon device having at least one differential pair pad, the at least one differential pair pad having a shunt inductor coupled thereon. A parasitic capacitance on at least one differential pair pads is tuned out by resonance of the shunt inductor. A package has a redistribution layer (RDL), with an array of contact areas to which the silicon device is mounted and then encapsulated. A connection corresponds to the at least one differential pair pad and the connection is located about an outer row or column of the array of contact areas.
US09576914B2
A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.
US09576913B2
A semiconductor device that improves noise performance includes a circuit substrate, an enclosing case, and a metal part. A control circuit is mounted on the front surface of the circuit substrate. The enclosing case is a resin case in which semiconductor elements are installed. The metal part, included inside the enclosing case, includes a first mounting portion, a second mounting portion, and a bus bar. The first mounting portion mounts the circuit substrate on the enclosing case, and is connected to a ground pattern of the circuit substrate when mounting. The second mounting portion mounts an external instrument on the enclosing case, and is grounded when mounting. The bus bar connects the first mounting portion and second mounting portion.
US09576901B1
A method for manufacturing a semiconductor device includes forming a contact area opening in a dielectric structure, depositing a contact area metal in the contact area opening, forming a metal cap layer on the contact area metal, forming one or more dielectric layers on the metal cap layer, forming one or more hard mask layers on the one or more dielectric layers, forming a metallization opening through the one or more dielectric and hard mask layers, wherein the metallization opening exposes the metal cap layer, removing the one or more hard mask layers, and forming a metallization layer in the metallization opening on the metal cap layer.
US09576900B2
A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation.
US09576891B1
An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.
US09576890B2
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained.As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
US09576885B2
A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.
US09576879B2
A heat-dissipation structure includes a first carbon nanotube layer and a thermal interface material layer. The first carbon nanotube layer and the thermal interface material layer are stacked on each other. The first carbon nanotube layer includes at least one first carbon nanotube paper, and the density of the first carbon nanotube paper ranges from about 0.3 g/cm3 to about 1.4 g/cm3. An electronic device applying the heat-dissipation structure is also disclosed.
US09576875B2
A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
US09576872B2
A method includes arranging multiple semiconductor chips over a first carrier and depositing a first material layer over surfaces of the multiple semiconductor chips, wherein depositing the first material layer includes a vapor deposition, and wherein the first material layer includes at least one of an organic material and a polymer.
US09576871B2
The present invention provides a composition of which viscosity does not cause the problem of use at high temperature in the mounting process of electronic device. The present invention relates to a composition for electronic device comprising (a) a (meth)acrylic compound and (c) a particle having a functional group having metal scavenging functionality.
US09576864B2
The present invention provides a short-circuit unit comprising: a plurality of signal lines divided into a plurality of groups, each group comprising multiple signal lines, and the multiple signal lines in a same group are not adjacent to each other; a plurality of short-circuit lines, each group of the signal lines correspond to one short-circuit line, and the short-circuit line electrically connects all of the signal lines in the group corresponding to the short-circuit line, the plurality of short-circuit lines are disposed in different layers and the short-circuit lines in different layers are insulated from each other. The present invention also provides an array substrate. In the short-circuit unit of the present invention, the short-circuit lines are disposed in different layers. Compared to the existing solutions in which the short-circuit lines are provided in a same layer, the width occupied by the short-circuit unit of the present invention is smaller.
US09576862B2
A system and method for identifying one or more characteristics of a structure formed into a substrate is herein disclosed. Surface and bulk acoustic waves are induced in the substrate and travel past a structure of interest where the acoustic waves are sensed. Information concerning one or more characteristics of the structure is encoded in the wave. The encoded information is assessed to determine the characteristic of interest.
US09576857B1
A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.
US09576856B2
Methods are presented for facilitating fabrication of nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate; providing first material layers and second material layers above the substrate, the first material layers interleaved with the second material layers; removing portions of the first material layers and second material layers, the removing forming a plurality of nanowire stacks, including first material nanowires and second material nanowires; removing the first material nanowires from at least one nanowire stack; and removing the second material nanowires from at least one other nanowire stack, where the at least one nanowire stack and at least one other nanowire stack include a p-type nanowire stack(s) and a n-type nanowire stack(s), respectively.
US09576853B2
A magnetic trap is configured to arrange at least one diamagnetic rod. The magnetic trap includes first and second magnets on a substrate that forms the magnetic trap defining a template configured to self-assemble diamagnetic material. Each of the first and second magnets extends along a longitudinal direction to define a magnet length, and contact each other to define a contact line. The first magnet and the second magnet have a diametric magnetization in a direction perpendicular to the contact line and the longitudinal direction so as to generate a longitudinal energy potential that traps the diamagnetic rod along the longitudinal direction.
US09576849B2
The semiconductor package includes semiconductor chips, each chip having one or more bonding pads. The semiconductor chips are stacked in a stepped configuration over the surface of the substrate without covering one or more bonding pads. An encapsulation member encapsulates the stacked semiconductor chips on the surface of the substrate. Via wirings in the encapsulation member electrically connect to a bonding pad of at least one of the semiconductor chips. Redistributions are formed over the encapsulation member such that the one or more redistributions are electrically coupled to the via wirings.
US09576847B2
Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.
US09576846B2
Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.
US09576841B2
A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
US09576839B2
A substrate carrier arrangement (10, 11) for a coating system (12) is provided, comprising a carrier (1) which comprises at least one support region (3) having a support surface (30), on which a substrate support (2) is arranged, and which support region comprises in the support surface (30) at least one first and one second gas inlet (4, 5), wherein the first gas inlet (4) is at a smaller distance from a center (M) of the support surface (30) than the second gas inlet (5) and wherein the first and second gas inlet (4, 5) comprise mutually independent gas feeds (40, 50) which are arranged to supply gases having mutually different thermal conductivities. A coating system comprising a substrate carrier arrangement and a method for performing a coating process are also provided.
US09576837B2
A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate.
US09576834B2
A stocker includes a storage shelf, an output-relay shelf, a first crane, an output shelf, a second crane, and a controller. The storage shelf has a plurality of storage spaces. The output-relay shelf has a plurality of first output-relay spaces. The output shelf has an output space. The controller is configured to drive the first crane to preferentially transfer a first wafer carrier stored in one of the storage spaces to an empty one of the first output-relay spaces according to a delivery command defining a high priority of the first wafer carrier, and configured to drive the second crane to preferentially transfer the first wafer carrier from the first output-relay space storing the first wafer carrier to the output space according to the delivery command if the output space is empty.
US09576826B2
Systems and methods for controlling wafer-breaker devices. In some embodiments, a controller for a semiconductor wafer singulation apparatus can be configured to receive an input signal having information about at least one singulation parameter. The controller can be further configured to generate an output signal based on the input signal to effectuate an operation associated with the singulation parameter. The controller can be further configured to disable manual control of the singulation parameter. In some embodiments, such a controller can be implemented, for example, in a control module, in a kit for modifying an existing singulation apparatus, as an integral part of a singulation apparatus, or any combination thereof.
US09576823B2
Shielded electronic packages may have metallic lead frames to connect an electromagnetic shield to ground. In one embodiment, a metallic lead frame of the electronic package and a surface of the metallic lead frame defines a component area for attaching an electronic component. The metallic lead frame includes a metallic structure associated with the component area that may have a grounding element for connecting to ground and one or more signal connection elements, such as signal leads, for transmitting input and output signals. The electromagnetic shield connects to the metallic lead frame to safely connect to ground while maintaining the signal connection elements isolated from the shield.
US09576818B2
Provided herein are polishing compositions for removal of Co, for example, selectively over Cu, and methods of their use. A polishing composition comprising an abrasive and one or more Co complexors, where the polishing composition has a pH of 9 or more, and the Co complexor comprises one or more of functional groups selected from phosphonic acid (—P(═O)(OH)2) group or carboxyl (—C(═O)OH) group.
US09576814B2
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.
US09576810B2
An apparatus configured to remove metal etch byproducts from the surface of substrates and from the interior of a substrate processing chamber. A plasma is used in combination with a solid state light source, such as an LED, to desorb metal etch byproducts. The desorbed byproducts may then be removed from the chamber.
US09576790B2
Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B, C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. One or more of the boron and carbon containing films can have a thickness of less than about 30 angstroms. Methods of doping a semiconductor substrate are provided. Doping a semiconductor substrate can include depositing a boron and carbon film over the semiconductor substrate by exposing the substrate to a vapor phase boron precursor at a process temperature of about 300° C. to about 450° C., where the boron precursor includes boron, carbon and hydrogen, and annealing the boron and carbon film at a temperature of about 800° C. to about 1200° C.
US09576785B2
An ignition facilitated electrodeless sealed high intensity illumination device is disclosed. The device is configured to receive a laser beam from a continuous wave (CW) laser light source. A sealed chamber is configured to contain an ionizable medium. The chamber has an ingress window disposed within a wall of a chamber interior surface configured to admit the laser beam into the chamber, a plasma sustaining region, and a high intensity light egress window configured to emit high intensity light from the chamber. A path of the CW laser beam from the laser light source through the ingress window to a focal region within the chamber is direct. The ingress window is configured to focus the laser beam to within a predetermined volume, and the plasma is configured to be ignited by the CW laser beam, optionally by heating of a non-electrode ignition agent located entirely within the chamber.
US09576776B2
The invention provides a charged particle sensor (10) for detecting and measuring ionic current generated by charged particles resulting from ionization processes, comprising: a housing (16), a detection electrode (14) enclosed within the housing for collecting the charged particles, and an electrometer (12) having an input connected to the detection electrode for receiving a DC input signal therefrom and an output (18) for supplying a DC measurement signal as output. The housing comprises an electrostatic screen (16) for screening the detection electrode from external electric fields, whereby to reduce the sensitivity of the detection electrode to such fields. The electrostatic screen includes an electrically conducting screening sheet (26) provided as a second electrode facing the detection electrode and formed with interstices to allow the entry of radiation into the housing, and the second electrode and the detection electrode are arranged to be maintained in use at a bias voltage with respect to one another so as to effect charge separation amongst charged particles resulting from ionization processes and thereby produce an ionic current impinging on the detection electrode.
US09576773B2
A method or process is disclosed for etching deep, high-aspect ratio features into silicon dioxide material layers and substrates, including glass, fused silica, quartz, or similar materials, using a plasma etch technology. The method has application in the fabrication and manufacturing of MEMS, microelectronic, micro-mechanical, photonic and nanotechnology devices in which silicon dioxide material layers or substrates are used and must be patterned and etched. Devices that benefit from the method described in this invention include the fabrication of MEMS gyroscopes, resonators, oscillators, microbalances, accelerometers, for example. The etch method or process allows etch depths ranging from below 10 microns to over 1 millimeter and aspect ratios from less than 1 to 1 to over 10 to 1 with etched feature sidewalls having vertical or near vertical angles. Additionally, the disclosed method provides requirements of the etched substrates to reduce or eliminate undesired effects of an etch.
US09576767B2
A focused ion beam system is provided. The focused ion beam system includes a plasma generation chamber configured to contain a source gas that is radiated with microwaves to produce plasma. The plasma generation chamber includes a plasma confinement device configured to confine the plasma in radial and axial directions within the plasma generation chamber and to form a plasma meniscus at an extraction end of the plasma generation chamber. The focused ion beam system also includes a beam extraction chamber configured to extract a focused ion beam from the confined plasma and to focus the extracted focused ion beam on a workpiece.
US09576759B2
A system and methods providing for minimizing the arc energy delivered to the pads of a plurality of contactors using a single control coil based on monitoring the electrical sine waves of the three alternating current electrical poles and calculating the instant to energize or deenergize a single control coil. The remainder of the contactors will make or break based on an offset in time from the making or breaking of the control contactor.
US09576757B2
Circuit interrupting devices, power distribution switchgear assemblies, and pole units for power distribution are provided. A circuit interrupting device includes a solid insulation housing, a disconnect, a window, and an insulating fluid. The solid insulation housing defines a first external opening and a first cavity extending into the solid insulation housing from the first external opening. The disconnect has a moving contact in selective engagement with a stationary contact in the first cavity. The window is secured to the solid insulation housing at the first external opening. The insulating fluid is disposed within the first cavity. The window, the solid insulation housing, or a combination thereof is configured to form a trap region that is in fluid communication with the first cavity and is configured to trap air bubbles in the insulating fluid.
US09576748B2
An electricity storage device includes an electricity storage element formed by winding an electrode body of an anode or cathode side along with a separator, an electrode leading section having an inclined edge is formed on an element end-face of the electricity storage element by a part of the electrode body.
US09576747B2
A hybrid energy storage device includes a positive pole including a supercapacitor first electrode and a battery positive electrode located in a same plane and contacts with each other, a negative pole including a supercapacitor second electrode and a battery negative electrode located in a same plane and contacts with each other, and a separator located between the positive pole and the negative pole. The supercapacitor second electrode, the battery negative electrode, the supercapacitor first electrode, the battery positive electrode, and the separator are planar structures. The supercapacitor first electrode, the supercapacitor second electrode, the battery positive electrode, the battery negative electrode, the separator and electrolyte are packaged in a shell.
US09576746B2
An energy storage module in which a plurality of energy storage cells including electrode terminals are stacked, includes a bus bar that electrically connects a plurality of electrode terminals, a conductive member that is secured on the bus bar, a detection section that detects a voltage of each of the energy storage cells, and a wiring board, a wire that is electrically connected to the detection section, and a pad that is connected to the wire being formed on the wiring board, the conductive member coming in contact with the pad.
US09576741B2
The present invention relates to a solid electrolytic capacitor and a production method thereof.A solid electrolytic capacitor of the present invention includes: a capacitor element having an anode wire inserted in one side surface thereof; a cathode terminal disposed on one side under the capacitor element to be electrically connected to the capacitor element; an anode terminal disposed on the other side under the capacitor element and having a bending portion integrally formed to be inclined to the capacitor element for electrical connection with the anode wire; and a molding portion surrounding the outside of the capacitor element and formed to expose lower surfaces of the cathode terminal and the anode terminal.
US09576740B2
A tantalum capacitor may include two tantalum wires exposed through two surfaces of a capacitor body opposing each other, first and second positive electrode terminals, connected to the tantalum wires, respectively, and disposed on two surfaces of a molded part opposing each other, and a negative electrode terminal disposed between the first and second positive electrode terminals. The negative electrode terminal may be electrically connected to the capacitor body by a via electrode or a pad electrode disposed between the negative electrode terminal and the capacitor body.
US09576734B2
An improved capacitor and method of making an improved capacitor is set forth. The capacitor has planer anodes with each anode comprising a fusion end and a separated end and the anodes are in parallel arrangement with each anode in direct electrical contact with all adjacent anodes at the fusion end. A dielectric is on the said separated end of each anode wherein the dielectric covers at least an active area of the capacitor. Spacers separate adjacent dielectrics and the interstitial space between the adjacent dielectrics and spacers has a conductive material in therein.
US09576733B2
An electronic component includes a capacitor having a desired capacitance value and a laminate including a plurality of laminated insulating material layers. Land electrodes are provided on a bottom surface of the laminate. Internal conductors face the land electrodes, respectively, across the insulating material layer within the laminate, have areas larger than those of the land electrodes, respectively, and contain the land electrodes, respectively, when seen in a planar view from a z-axis direction. A capacitor conductor is provided on the positive direction side of the capacitor conductors in the z-axis direction and faces the capacitor conductors.
US09576728B2
A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.
US09576725B2
Systems and methods are disclosed for reducing an interwinding capacitance current in a transformer. In certain embodiments, the transformer includes a coupling winding and a primary winding that encircles a portion of the coupling winding. Additionally, the transformer includes a secondary winding that encircles a portion of the coupling winding. The transformer includes a shield terminal which is electrically coupled to the coupling winding. The shield terminal directs currents, such as interwinding capacitance currents, in the coupling winding to ground.
US09576719B2
Embodiments of an electromagnetic coil assembly are provided, as are methods for the manufacture of an electromagnetic coil assembly. In one embodiment, the method for manufacturing an electromagnetic coil assembly includes the steps of providing a braided aluminum lead wire having a first end portion and a second end portion, brazing the first end portion of the braided aluminum lead wire to a first electrically-conductive interconnect member, and winding a magnet wire into an electromagnetic coil. The second end portion of the braided aluminum lead wire is joined to the magnet wire after the step of brazing.
US09576711B2
There are provided a coil component and a board having the same. The coil component includes: a magnetic body including a substrate having two cores, first and second coil parts disposed on one surface of the substrate and wound in the same direction, and third and fourth coil parts disposed on the other surface of the substrate to be spaced apart from each other; and first to fourth external electrodes disposed on outer surfaces of the magnetic body and connected to the first to fourth coil parts.
US09576709B2
A transformer is provided having a stacked core with a pair of outer legs extending between a pair of yokes. The core is arranged in a plurality of layers. Each of the layers includes a pair of yoke plates and a pair of outer leg plates. In an inner-most layer, the width of each yoke plate is less than the width of each outer leg plate. In each of the layers, the inner points of the outer leg plates are substantially in contact with the yoke plates. The cross-section of the inner leg and the outer legs may be rectangular or cruciform.
US09576705B2
There is provided a support module of a sleeve for a transmission line, which is inserted into a part of a plurality of accommodation spaces formed at a flexible sleeve for a transmission line to prevent the sleeve for a transmission line from being slack, including a flexible flat plate; a plurality of bases fixed to the flat plate so as to be arranged in a longitudinal direction of the flat plate; a plurality of slack-preventing blocks that is connected to the bases to be positioned at a top of the flat plate and prevents the flat plate from being slack by coming in contact with each other; and a plurality of bending-degree restricting blocks that is connected to the bases and the slack-preventing blocks to be positioned a bottom of the flat plate and restricts a bending degree of the flat plate by coming in contact with each other.
US09576698B2
A method for forming a polyimide-carbon nanotube composite film on a substrate is provided. The method comprises: suspending carbon nanotubes in a solution comprising a poly(amic acid) and a suitable solvent; casting the solution onto a substrate to form a layer on the substrate; and heating the layer to convert the poly(amic acid) into a polyimide to form the polyimide-carbon nanotube composite film. A polyimide-carbon nanotube composite film and an electronic device comprising the polyimide-carbon nanotube composite film are also provided.
US09576697B2
A multilayer electronic component may include a multilayer body including a plurality of magnetic material layers, and an internal electrode disposed in the multilayer body. The internal electrode may contain a conductive metal and glass, and the glass contains a vanadium (V) oxide.Also, a conductive paste composition for an internal electrode includes a conductive metal and glass, wherein the glass contains a vanadium (V) oxide.
US09576681B2
A semiconductor device includes a semiconductor device, comprising a memory cell array including a plurality of memory cells connected to a first bit line and a second bit line, respectively, a page buffer group, and bit line selection circuits including a plurality of selection circuit blocks to connect the first bit lines or the second bit lines to the page buffer group, wherein each of the selection circuit blocks includes a first contact region and a second contact region to which the first and second bit lines coupled, and same bit lines of the first and second bit lines are coupled to contact regions adjacent to one another of the first and second contact regions included in bit line selection circuits adjacent to one another of the bit line selection circuits.
US09576679B2
A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node.
US09576678B2
A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.
US09576675B2
A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
US09576672B2
A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.
US09576670B1
An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.
US09576662B2
Subject matter disclosed herein relates to management of a memory device.
US09576660B2
A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
US09576641B2
Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.
US09576628B1
A semiconductor device may include a driving control signal generation circuit configured to generate a driving control signal by determining whether a corresponding operation is a gapless read operation, according to a read strobe signal. The semiconductor device may also include a power driving circuit configured to drive a supply voltage to a power supply voltage in response to the driving control signal, and a read control signal generation circuit configured to generate a read control signal for controlling a read operation from the read strobe signal in response to the supply voltage.
US09576621B2
A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.
US09576614B2
A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
US09576608B2
In one embodiment, an apparatus may include a processor circuit and a keyframe indexing module that is operative on the processor circuit to map sensor data from a first sensor to a set of video data, where the sensor data and video data correspond to an event. The keyframe indexing module may be further operative on the processor circuit to identify one or more key portions of the set of sensor data, index the one or more key portions to respective mapped one or more video frames of the video data, and generate a first keyframe index to identify the one or more video frames.
US09576605B2
A magnetic disk apparatus includes a disk and a controller. The disk includes a plurality of tracks including a first track and a second track that is different from the first track. A plurality of data sectors are located on the tracks. The data sectors include short data sectors and long data sectors, each including a plurality of short data sectors. If the controller accesses a long data sector located at an end of the first track, the controller first accesses a short data sector of the long data sector at the end of the first track, and then accesses a short data sector of the long data sector at the beginning of the second track.
US09576602B2
A flexure for mounting a plurality of reproduction elements thereon includes a metal base and an interconnection part. The metal base includes a first area, and a second area in which a window portion is formed. The interconnection part includes an insulating layer including a first lane which covers the first area and a second lane which covers the second area, a write trace pair connected to a recording element, read trace pairs provided on the second lane to face the window portion and connected to reproduction elements, respectively, and a ground trace arranged between two adjacent read trace pairs and provided with grounding points at two end portions.
US09576596B2
In one general embodiment, an apparatus includes a magnetic head. The magnetic head has a first portion and a second portion, the first portion and the second portion together providing a tape bearing surface. The first portion has an opening at least partially encircling the second portion. The second portion has two modules, each module having at least one array of transducers. Each module has a first outermost edge oriented orthogonally to an intended direction of tape travel thereacross, and a second outermost edge opposite the first edge, the second edge being oriented at an angle between 0.2° and about 10° relative to a line oriented orthogonally to the intended direction of tape travel thereacross.
US09576592B2
A communication system according to the present invention includes a plurality of terminal devices that are able to communicate mutually. Each of the terminal devices includes a voice input conversion device, a voice transmitting device, a voice receiving device, and a voice reproducing device. When there is a plurality of voice signals which has not been completed reproduction, the voice reproducing device reproduces after arranging the voice signals so that respective voices corresponding to the respective voice signals do not overlap.
US09576590B2
An apparatus comprising at least one processor and at least one memory including computer code for one or more programs, the at least one memory and the computer code configured to with the at least one processor to cause the apparatus to at least perform: estimating a signal to noise ratio value for an audio signal; generating a post-filter comprising at least one of: a first formant frequency filter and a second formant frequency filter, wherein the post-filter is dependent on the signal to noise ratio value for the audio signal.
US09576588B2
A close-talk detector detects a near-end user's speech signal, while an adaptive ANC process is running, and in response helps prevent the filter coefficients of an adaptive filter of the ANC process from being corrupted, thereby reducing the risk of the adaptive filters diverge. Upon detecting speech using a vibration sensor signal and one or more microphone signals, the detector asserts a signal that slows down, or even freezes or halts, the adaptation of the adaptive filter. The signal may be de-asserted when no more speech is being detected, thereby allowing the adaptive ANC process to resume its normal rate adaptation of the filter. The detector may continuously operate in this manner during the call, as the user talks and then pauses and then resumes talking. Other embodiments are also described.
US09576583B1
We describe techniques for restoring an audio signal. In embodiments these employ masked positive semi-definite tensor factorization to process the signal in the time-frequency domain. Broadly speaking the methods estimate latent variables which factorize a tensor representation of the (unknown) variance/covariance of an input audio signal, using a mask so that the audio signal is separated into desired and undesired audio source components. In embodiments a masked positive semi-definite tensor factorization of ψftk=MftkUfkVtk is performed, where M defines the mask and U, V the latent variables. A restored audio signal is then constructed by modifying the input signal to better match the variance/covariance of the desired components.
US09576582B2
Disclosed herein are systems, computer-implemented methods, and computer-readable storage media for recognizing speech by adapting automatic speech recognition pronunciation by acoustic model restructuring. The method identifies an acoustic model and a matching pronouncing dictionary trained on typical native speech in a target dialect. The method collects speech from a new speaker resulting in collected speech and transcribes the collected speech to generate a lattice of plausible phonemes. Then the method creates a custom speech model for representing each phoneme used in the pronouncing dictionary by a weighted sum of acoustic models for all the plausible phonemes, wherein the pronouncing dictionary does not change, but the model of the acoustic space for each phoneme in the dictionary becomes a weighted sum of the acoustic models of phonemes of the typical native speech. Finally the method includes recognizing via a processor additional speech from the target speaker using the custom speech model.
US09576575B2
A method for determining a voice command shortcut includes receiving a first voice command providing instructions for performing a particular task and a second voice command providing additional instructions for performing the same task. The voice command shortcut may be used in place of the first and second voice commands, which are typically submitted in response to system prompts. The availability of a voice command shortcut is determined based on the first and second voice commands. If a voice command shortcut is available, an audible and/or visual notification may be provided to inform the user of the available voice command shortcut.
US09576570B2
The present invention relates to a method and apparatus for adding new vocabulary to interactive translation and dialog systems. In one embodiment, a method for adding a new word to a vocabulary of an interactive dialog includes receiving an input signal that includes at least one word not currently in the vocabulary, inserting the word into a dynamic component of a search graph associated with the vocabulary, and compiling the dynamic component independently of a permanent component of the search graph to produce a new sub-grammar, where the permanent component comprises a plurality of words that are permanently part of the search graph.
US09576569B2
A playback control apparatus includes a playback controller configured to control playback of first content and second content. The first content is to output first sound which is generated based on text information using speech synthesis processing. The second content is to output second sound which is generated not using the speech synthesis processing. The playback controller causes an attribute of content to be played back to be displayed on the screen, the attribute indicating whether or not the content is to output sound which is generated based on text information using speech synthesis processing.
US09576553B2
A method and apparatus for producing a reflective or refractive surface that reflects or refracts light shined thereon and reproduces on a screen a desired greyscale intensity image on which the reflective or refractive surface is based and a corresponding apparatus, wherein the method permits a reproduction of a reference grayscale image with adjustable precision.
US09576549B2
According to one embodiment, an electronic apparatus, includes a sensor-equipped display device includes a display device and a sensor configured to detect a contact or proximate position, a display driver configured to output an image display signal to the display device and to output a drive signal to the sensor, a detecting circuit configured to generate, based on the information from the sensor, raw data (Raw data) including three-dimensional information of coordinates of a position on the display device and a physical quantity at the coordinates, and an application processor configured to discriminate whether a part of the region in the display area should be further sensed or not, based on the raw data, and if the part of the region is further sensed, to output the range of the display device to be further sensed and the timing of driving the sensor to the display driver.
US09576548B2
A touch panel is disclosed. The touch panel is detects a position of a stylus, which includes first and second resonance circuits. The touch panel includes first and second coils respectively extending in first and second directions. Each of the first coils emits a first signal having a first frequency and receives a second signal having a second frequency, where emitting the first signal and receiving the second signal are successively and respectively performed by the plurality of second coils. In addition, each of second coils emits a second signal having the second frequency and receives a first signal having the first frequency, where emitting the second signal and receiving the first signal are successively performed. The first resonance circuit of the stylus generates the first signal after receiving the first signal, and the second resonance circuit of the electromagnetic stylus generates the second signal after receiving the second signal.
US09576528B2
A method of manufacturing a display unit in which the method includes: forming a transistor on a substrate, in which a first direction to be scanned by an ion implantation apparatus intersects with a second direction to be scanned by an Excimer Laser Anneal apparatus; and forming a display element.
US09576526B2
A semiconductor device in which a transistor can supply an accurate current to a load (EL pixel and signal line) without being influenced by variations is provided.A voltage at each terminal of a transistor is adjusted by a feedback circuit using an amplifier circuit. A current Idata is input from a current source circuit to the transistor, and a gate-source voltage is set by the feedback circuit so that the transistor can flow the current Idata. The feedback circuit controls the transistor to operate in a saturation region. Thus, a gate voltage required for flowing the current Idata is set. With the use of the set transistor, a current can be supplied to a load (EL pixel and signal line) with accuracy. Note that a desired gate voltage can be set quickly since the amplifier circuit is utilized.
US09576525B2
Provided are an AMOLED pixel unit, a method for driving the same, and a display device. The AMOLED pixel unit includes a compensating unit, a light emitting control unit, a driving transistor, a storage capacitor and an organic light emitting diode, wherein the compensating unit is switched on under the control of a signal on a scan line; the light emitting control unit is switched on under the control of a signal on a light emitting control line; an anode of the organic light emitting diode is connected to a second terminal of the storage capacitor, and a cathode of the organic light emitting diode receives a second power supply signal. Such a circuit can effectively compensate for the drift and the non-uniformity of the threshold voltages of the transistors and the non-uniformity of the voltages of the organic light emitting diodes.
US09576519B2
The invention provides a display method and a display device. The display method in the invention is applicable to a display panel comprising multiple rows of sub-pixels, each row of sub-pixels are formed of sub-pixels of various colors which are alternately and circularly arranged, the sub-pixels in each row are arranged in the same order, and in column direction, sub-pixels of the same color are not adjacent, wherein the display method comprises steps of: S1, generating a primary image based on image information, the primary image is formed of virtual pixels arranged in a matrix, each virtual pixel is formed of sub-pixels of different colors and size of the virtual pixel is the same as that of the sub-pixel of the display panel; S2, calculating a display component of each sub-pixel by using primary components of sampling virtual sub-pixels of the sub-pixel.
US09576515B2
A bright dot detection method adapted to be used in a display panel including a plurality of gate lines, a plurality of source lines and a bright dot detection module. The plurality of gate lines and the plurality of sources line are interlaced thereby forming a plurality of pixels. The bright dot detection method includes: driving the plurality of pixels through enabling the plurality of gate lines simultaneously, thereby forming a first bright line in a first direction; and driving the plurality of pixels through enabling the plurality of gate lines sequentially and providing a control signal to the bright dot detection module, thereby forming a second bright line in a second direction, wherein a bright dot is positioned where the first and second bright lines meet with each other. A display panel is also disclosed.
US09576514B2
A detecting method and a detecting apparatus for detection of a gate line disconnection. The gate line disconnection detecting method includes step 1: providing a first unit (41) at least capable of receiving signals at one end of a gate line to be detected (2), and providing a second unit (42) at least capable of transmitting signals at the other end of it; step 2: providing a first signal receiving unit (51) for receiving signals on a gate line other than the gate line to be detected (2). With respect to the gate line disconnection detecting method, whether disconnection occurs or not is judged depending on the signal strength received by the first signal receiving unit (51), and thus, the case that in a gate line disconnection detection of a bilateral drive type display device, whether a gate line is disconnected or not can be accurately detected, is realized. By it, technical supports are provided for getting rid of bad products timely, and a goal of promoting the yield of products is achieved.
US09576512B2
A display panel including a display part including a plurality of sub-pixels configured to display a plurality of colors, and a plurality of data lines connected with the sub-pixels; a first test part configured to supply a test signal to (2K−1)th data lines (‘K’ is an integer above 0) by each color for the sub-pixels among the plurality of data lines; and a second test part configured to supply a test signal to 2Kth data lines by each color for the sub-pixels among the plurality of data lines when the first test part supplies the test signal. Further, a polarity of the test signal supplied by the second test part is opposite to a polarity of the test signal supplied by the first test part.
US09576501B2
In one aspect, a device includes a processor, a display accessible to the processor, and memory accessible to the processor. The memory bears instructions executable by the processor to provide sound corresponding to a portion of text presented on the display with at least one portion of the sound being provided as if originating at least substantially from a location on the display at which the portion of text is presented on the display.
US09576500B2
A training supporting system has a training supporting apparatus and an exercise form analyzing apparatus, the both apparatuses being connected to each other through a communication network. The training supporting apparatus is worn on the arm of a user and measures acceleration rates of motion of the user's body where the apparatus is fitted on, at least in the three directions along X-, Y- and Z-axes, while the user is walking or running. Receiving the measured acceleration rates from the training supporting apparatus through the communication network, the exercise form analyzing apparatus analyzes an exercise form including balance between arm swing and foot landing, and sends back the analysis result of the exercise form to the training supporting apparatus through the communication network.
US09576499B2
A system for delivering targeted content based on user behavior stores multiple behavior change models, generates a user record containing information regarding a user, selects a behavior change model from the multiple stored models based on the information in the user record, and delivers to the user targeted content based on the selected behavior change model, the targeted content being adapted to influence the user to change behavior according to the selected behavior change model.
US09576488B2
Animation and visualization of roadway performance analytics in a dashboard presentation in an integrated performance measurement system comprises analyzing collected traffic data to generate measured congestion information that reflects current conditions in one or more links, segments, or corridors comprising a roadway. The measured congestion information is presented in one or more sets of indicia on a graphical user interface so that current congestion conditions can be viewed and analyzed by a user. The measured congestion information is represented as gauges displaying percentage increases or decreases relative to a particular time, as animated maps showing a selectable set of current congestion conditions, as one or more graphs of current congestion conditions over time, as chart-based displays of costs and causes of current congestion conditions, and a data feed listing textual live updates.
US09576484B2
A system and method for monitoring vehicular traffic with a laser rangefinding and speed measurement device utilizing a shaped divergent laser beam pattern. In accordance with the present invention, a traffic monitoring device is disclosed which comprises a light emitting diode having a die element producing an asymmetric beam pattern, an aperture for at least partially precluding some portion of the beam pattern in a first direction while allowing the beam pattern in a second orthogonal direction to pass therethrough and a lens associated with the aperture for causing the laser beam exiting the aperture to diverge providing a cone-like beam of laser energy.
US09576482B2
A system comprising a plurality of mobile object servers respectively assigned to a plurality of regions in a geographic space, the plurality of mobile object servers including at least one mobile object server including a mobile object agent assigned to a moving object in the assigned region; and a plurality of event servers operable to manage events occurring in the geographic space; wherein each mobile object server is operable to transfer the mobile object agent to one of the plurality of mobile object servers assigned to a neighboring region in response to the moving object moving to the neighboring region, and execute the mobile object agent to collect information of events from at least one event server, and provide the moving object with information that assists the moving object with traveling in the geographic space.
US09576474B2
A method and a system for providing vehicle services to at least one communication device located at a vehicle via a vehicle telematics unit. The method carried out by the system includes the steps of: receiving a request at the vehicle telematics unit for first vehicle services from a first communication device located at a vehicle; associating a first identifier with the first communication device; and providing the first vehicle services to the first communication device, wherein the vehicle services are provided according to at least one services parameter associated with the first identifier.
US09576471B2
A radio frequency (RF) remote controller device comprises radio frequency (RF) circuitry operably coupled to an antenna arrangement and arranged to transmit and receive RF signals to and from controllable devices. The RF remote controller device further comprises signal process logic operably coupled to the RF circuitry and to a user interface. The antenna arrangement is arranged to comprise a directivity characteristic. The signal processing logic upon receipt of a command input from the user interface, is arranged to: determine at least one link quality value that is at least partly dependent upon the directivity characteristic for the at least one controllable device; and select the controllable device for remote controlling based on the determined at least one link quality value.
US09576470B2
A combination of an articulated apparatus having an electromechanical actuator, a power supply and a control unit with a unique electronic address, and a cordless controller, the cordless controller becoming exclusively electrically paired to the articulated apparatus when common signals therefrom to the control box include the unique electronic address, thus enabling control of the articulated apparatus when located near the other apparatus having other electronic addresses.
US09576456B2
A reception unit 2 of a detection unit 3 includes a transmitter 30 that transmits a reception (detection) level of an infrared beam to a transmission unit 1, and a demand signal output unit 26 that transmits to the transmission unit 1 a demand signal M, demanding to control the intensity of the infrared beam to be transmitted so that the reception level matches a predetermined value. The transmission unit 1 includes an infrared ray (detection beam) intensity control unit 15 that controls, upon receipt of the demand signal M, the intensity of the infrared beam to be transmitted so that the reception level matches the predetermined value. A power source unit 31 is a solar battery unit including a solar panel and a charging medium that stores power from the solar panel.
US09576455B2
A system and method provides access to antennas of an electronic article surveillance system via WiFi and the Internet. Each antenna of the EAS system has a WiFi chip associated with its controls and the WiFi chip relays the antennas operating parameters as well as its reading of electromagnetic noise in its environment to the Internet. A remote technician can review the information provided by the antennas of the EAS system and optimize their operation with each other and their environments. In some embodiments, remote software can optimize the operation of the EAS system antennas. In some embodiments, the WiFi chip is an aftermarket addition.
US09576446B2
A haptic switch includes: (a) a force sensor responding a mechanical stimulus by providing a sensing signal; (b) a processing circuit receiving the sensing signal and providing a control signal; and (c) an electromechanical polymer (EMP) actuator receiving the response control signal and providing a haptic response. The force sensor and the EMP actuator may each be provided on a flexible circuit covered by a protective layer overlying the flexible circuit. The haptic switch may include a graphic layer on which is provided a symbol representing a key. In that haptic switch, the symbol, the light source, the EMP actuator and the force sensor are aligned such that the light source illuminates the symbol and such that, when a user pushes on the symbol, the user's push applies a pressure on the force sensor and the EMP actuator's haptic response is provided in the vicinity of the force sensor.
US09576445B2
Systems and methods for generating haptic effects associated with envelopes in audio signals are disclosed. One disclosed system for outputting haptic effects includes a processor configured to: receive an audio signal; determine an envelope associated with the audio signal; determine a haptic effect based in part on the envelope; and output a haptic signal associated with the haptic effect.
US09576443B2
Systems and method of providing beacon-based notifications are provided. More particularly, an identifying signal can be received from a beacon device. A geographic location of a user device can be determined based at least in part on the identifying signal. At least a portion of time-based contextual beacon data can then be obtained based at least in part on spatial-temporal data associated with a user. One or more notifications associated with the contextual beacon data can then be determined. The one or more notifications can indicative of information corresponding to the beacon device, and can be provided for display on a user device.
US09576437B2
Systems, apparatuses and methods for enhancing winning result opportunities in poker gaming activities. Embodiments involve identifying award-enhancing opportunities using dice to determine award-enhancing opportunities based on the dice results for a poker game played on a gaming device. Award-enhancing opportunities can be accumulated during multiple bonus rounds, or single bonus rolls of dice may be used to determine multipliers or other modifiers to enhance awards received in the poker games.
US09576432B2
A game is executed in a normal round, in a first-type free round, and in a second-type free round. The normal round is executed with a first symbol set including a plurality of symbols. The first-type free round is executed with a second symbol set that includes at least one first symbol in addition to the symbols in the first symbol set. The second-type free round is executed with a third symbol set that includes at least one second symbol in addition to the symbols in the first symbol set, the at least one second symbol being different from the at least one first symbol.
US09576431B2
Systems, apparatuses and methods for enhancing winning result opportunities in gaming activities. Embodiments involve identifying award-enhancing opportunities using dice, and enabling repetition of such award-enhancing opportunities based on the dice results until a terminating event occurs using the die/dice. Award-enhancing opportunities can be accumulated during the repetition, whereby payout opportunities of the gaming event from which the dice activity was initiated may be enhanced.
US09576429B2
Systems, methods, and articles of manufacture provide for site-wide and/or community jackpots.
US09576425B2
In one embodiment, an intermediary gaming trusted electronic device for use with an untrusted PED may include a position sensor configured to acquire position information, a memory configured to store at least game session data, and a processor configured to at least: securely communicate with a gaming apparatus via the wireless transceiver; securely communicate with the associated untrusted PED; determine whether a gaming session is permitted based on the position information; receive gaming data from the gaming apparatus if it is determined that the gaming session is permitted; transmit presentation data to the associated untrusted PED for presentation on a display of the associated PED, wherein the intermediary gaming trusted device is able to support interaction between the gaming apparatus and the associated untrusted PED so that the associated untrusted PED, when coupled to the intermediary gaming trusted device, can execute a gaming software.
US09576424B2
Systems for making a side bet in a hybrid game having a gambling game portion and an entertainment game portion are provided. The side bet is made in regards to the play of the entertainment portion of the hybrid game and can be made using a real world credit, a game world credit or a game world element. If the side bet is made using a real world credit, the real world credits used by the gambling game portion of the hybrid game and credited to a player are incremented or decremented. If the side bet is made using a game world element, the entertainment game portion of the hybrid game is updated based on the outcome of the side bet.
US09576420B2
A gaming device incentivizes additional game play by combining payouts with conditional payouts. During game play, players are informed of the conditions, which must be satisfied so as to vest the conditional payouts. Subsequent game play is monitored to see if the player has satisfied the conditions. If the player has satisfied the conditions, then the conditional payout vests. If the condition is not met, then the conditional payout terminates.
US09576417B2
According to some example embodiments, systems, apparatus, methods, computer readable media, and computer program products are provided for implementing an item pusher apparatus with channel-based shuttle displacement detection. One example method includes determining a position of a channel engagement member affixed to a shuttle, where the shuttle is movable and configured to at least exert a force on an item to urge the item towards a stopping member. The channel engagement member is configured to at least physically interface with as channel defined such that movement of the shuttle alone a defined movement path causes movement of the channel engagement member in a direction that is nonparallel to the defined movement path in at least one plane. Example systems apparatuses, methods, computer readable media, and computer program products are also provided.
US09576409B2
A device includes a device body having an attachment face defined by an attachment area and a contact array disposed in the device body and exposed at a coupling face. The contact array comprises one or more magnets disposed on the coupling face and a plurality of terminals disposed on the coupling face. A periphery of the one or more magnets and the plurality of terminals defines a coupling area. The attachment area is greater than and independent of the coupling area.
US09576404B2
A system for transmitting aircraft data from an aircraft includes a Data Acquisition Unit (DAU) that records aircraft data. A PC card is interfaced to the DAU and stores the aircraft data from the DAU. A processor retrieves aircraft data from the memory. A first wireless transceiver is controlled by the processor and receives and transmits the aircraft data along a wireless communications signal. A wireless local area network (LAN) communications unit is configured as an access point and positioned within the aircraft and transmits and receives wireless communications signals to and from the PC card. A second wireless transceiver is mounted within the aircraft and receives the wireless communications signal from the wireless LAN communications unit for transmitting the aircraft data from the aircraft.
US09576403B2
A method and an apparatus for improving a main image by fusing the richer information contained in a secondary image are described. A 3D structure of objects contained in the secondary image is retrieved and a parallax-corrected version of the secondary image is generated using the 3D structure. For this purpose a camera pose for which a projection of the 3D structure of the objects contained in the secondary image best resembles the perspective in the main image is determined and the parallax-corrected version of the secondary image is synthesized based on the determined camera pose. The parallax-corrected version of the secondary image is then fused with the main image.
US09576401B2
A method of creating an interlaced composite image. The method comprises receiving a plurality of images selected for generating an interlaced composite image by interlacing a plurality of image strips from each image, providing a filter as a function of an approximate inverse transform of an undesired distortion dataset representing at least one estimated undesired distortion caused by an autostereoscopic display element when a user views the interlaced composite image via the autostereoscopic display element, generating a reduced artifact interlaced composite image by applying the filter on the plurality of images, and outputting the reduced artifact interlaced composite image.
US09576387B2
An apparatus receives first image data that is based on image data captured by a first camera and second image data that is based on image data captured by a second camera. The apparatus then creates a cinemagraph using the first image data for a static part of the cinemagraph and using the second image data for an animated part of the cinemagraph. Another apparatus could provide at least one of the first and second image data based on a detected corresponding element.
US09576383B2
A first chart and a second chart are parsed to determine one or more measures, dimensions, and filters visualized in the first chart and the second chart. The number of measures, dimensions, and filters visualized in the first chart and the second chart are calculated. It is determined how many of the number of measures, dimensions, and filters visualized in the first chart and the second chart are the same. One or more merge rules corresponding to the number of measures, dimensions, and filters visualized in the first chart and to the number of measures, dimensions, and filters visualized in the second chart that aren't the same as measures, dimensions, and filters visualized in the first chart are obtained, and one or more merge permutations are derived based on the obtained merge rules. The first chart and the second chart are merged in accordance with one of the merge permutations.
US09576375B1
Systems and methods of detecting dead pixels of image frames are described including receiving a sequence of image frames, aligning, from the sequence of image frames, pairs of image frames, and for a given pair of image frames, determining differences in intensity of corresponding pixels between the aligned pair of image frames. The method also includes, based on the differences in intensity of corresponding pixels between the aligned pair of image frames, generating mask images indicative of areas in the pairs of image frames having moving objects. The method further includes determining, within the mask images, common pixel locations indicative of areas in the pairs of image frames having moving objects over a portion of the sequence of image frames, and based on a number of the common pixel locations for a given pixel location being above a threshold, identifying the given pixel location as a dead pixel.
US09576373B2
A geospatial imaging system may include a geospatial data storage device configured to store a geospatial dataset including geospatial data points. A processor may cooperate with the geospatial data storage device to determine segments within the geospatial dataset, with each segment including neighboring geospatial data points within the geospatial dataset sharing a common geometric characteristic from among different geometric characteristics. The processor may further determine border geospatial data points of adjacent segments, compare the border geospatial data points of the adjacent segments to determine bare earth segments having respective heights below those of the border geospatial data points of adjacent segments, and classify geospatial data points within each bare earth segment as bare earth geospatial data points.
US09576366B2
A tracking system and method using the same is disclosed which is capable of minimizing a restriction of surgical space by achieving a lightweight of the system as well as a reduction of a manufacturing cost through calculating a three-dimensional coordinates of each of makers using one image forming unit. In the tracking system and method using the same, lights emitted from the markers are transferred to one image forming unit through two optical paths, an image sensor of the image forming unit forms two images (direct image and reflection image) of the two optical paths of the markers, and therefore, the system and method using the same has an effect of reducing a manufacturing cost of the tracking system with small and lightweight, and relatively low restriction of surgical space comparing with conventional tracking system since it is possible to calculate a spatial position and direction of the markers attached on a target by using one image forming unit.
US09576365B2
Provided is a method of aligning a camera using correspondence information between multi-images. The camera alignment method using correspondences between multi-images includes defining a correspondence relation between images photographed in the multi-camera system, estimating an initial position of the camera using the correspondence relation between the images and a Structure From Motion (SFM) algorithm, redefining a changed correspondence relation between the images as a result of the estimation of the initial position of the camera using a bundle edge to generate an optimal edge, and correcting the position of the camera based on the optimal edge.
US09576360B2
Method for assessing a regurgitant flow through a valve into a moving object from a sequence of consecutive image frames of such object, which images are timely separated by a certain time interval, the method comprising the following steps: a) identifying in the images the object of interest; b) augmenting the images to compensate for protocol intensity variation and/or motion and/or background; c) making a time-analysis of augmented images to obtain time-density curve or curves, wherein time-density curves represent a time-evolution of pixel brightness; d) determining a plurality of parameters related to such time-density curve or curves; e) weighting such parameters to provide indications on the regurgitant flow. A corresponding apparatus and computer program are also disclosed.
US09576351B1
Techniques are disclosed for automatically transferring a style of at least two reference images to an input image. The resulting transformation of the input image matches the visual styles of the reference images without changing the identity of the subject of the input image. Each image is decomposed into levels of detail with corresponding energy levels and a residual. A style transfer operation is performed at each energy level and residual using the reference image that most closely matches the input image at each energy level. The transformations of each level of detail and the residual of the input image are aggregated to generate an output image having the styles of the reference images. In some cases, the transformations are performed on the foreground of the input image, and the background can be transformed by an amount that is proportional to the aggregated transformations of the foreground.
US09576344B2
In order to make it possible to reduce the storage capacity required for noise removal processing in, for example, multi-resolution analysis and the like, without affecting signal quality, the present invention is equipped with: a storage device into which a input signal of a first channel is written, the input signal branching off into at least first and second channels; a first frequency transform processing unit which transforms the input signal read out and inputted from the storage device into a frequency-domain to output a first signal; a second frequency transform processing unit which transforms the input signal inputted from the second system into a frequency-domain to output a second signal; a third frequency transform processing unit which transforms the second input signal inputted from the second frequency transform processing unit into a frequency range to output a third and fourth signals in the first and second frequency bands; a first inverse frequency transform processing unit; and a second inverse frequency transform processing unit to which directly or indirectly inputting the third signal from the third frequency transform processing unit is directly or indirectly inputted and the fourth signal from the third frequency transform processing unit is inputted, and which outputs a third transformed signal produced through performing inverse frequency transform on the inputted signals. Therein, the first inverse frequency transform processing unit, to which the first signal from the first frequency transform processing unit is directly or indirectly inputted and the third converted signal from the second inverse frequency transform processing unit is directly or indirectly inputted, outputs a signal produced through performing inverse frequency transform on the inputted signals.
US09576337B2
An image processing apparatus is provided. The image processing apparatus includes an image quality processor and a controller. The image quality processor performs a detail enhancement function on an image frame. The controller calculates blur information and/or gray information of the image frame and controls the image quality processor to perform the detail enhancement function on the image frame based on the calculated information.
US09576330B2
A virtual world environment unit, and related methods, operable to simulate an actual live event in substantially real-time is disclosed. Also disclosed is an interactive media system configured to present a substantially real-time simulation of an actual live event involving a moveable object in an arena. Further disclosed is a method of providing and/or viewing a substantially real-time simulation of an actual live event involving a moveable object in an arena
US09576326B2
Techniques for identification of a propagator-type leader in a social network are described. According to various embodiments, a specific content item posted by a particular actor of a plurality of actors and interactions by other actors of the plurality of actors with the specific content item are identified. A leadership score associated with the particular actor is calculated, the leadership score indicating a propensity of the particular actor to spread information among the plurality of actors of the online social network service. The particular actor is then classified as an information propagator among the plurality of actors of the online social network service, based on the calculated leadership score.
US09576325B2
Social networking system users may create events where a group of other users invited to the event meet at a specified time and location. While an inviting user initially specifies the group of users to invite to the event, the social networking system suggests additional users to invite to the event. The social networking system suggests additional users based on a prediction that the users would attend the event if invited. Various factors may be used to make the prediction, such as an affinity between the inviting user and the other users, the availability of the other users at the time of the event and/or the proximity of the other users to the location of the event. Invitations to the suggested additional users may be automatically sent or sent to a set of the additional users selected by the inviting user.
US09576321B2
A system and method for supporting the purchase of products offered for sale. The system and method may include delivering for display to a buyer information regarding the product being offered for sale, along with retrieving profile information relating to the potential buyer from one or more other systems, for use in consummating the purchase of the product.
US09576319B2
Automatic trading environments with their high degree of automation have become the backbone of modern financial markets. The ability to process orders and manage risk in these systems while maintaining a low latency between participants is crucial for the safety and liquidity of these markets. The disclosed system describes a four valued Monte Carlo simulation for the stochastic modeling of risk and syntactic pattern matching techniques to facilitate the design of these systems. The system is a self-compiling, machine independent system capable of dividing, scaling and communicating multiple-asset instruments efficiently in a parallel environment. The system also allows for the integration of computerized financial heuristics on financial instruments and user interfaces for creating trading strategies to monitor and hedge risk over a trading desk for financial institutions.