US09236609B2
A positive active material for a rechargeable lithium battery includes a nickel-based composite oxide represented by the following Chemical Formula 1, wherein the nickel-based composite oxide includes an over lithiated oxide and non-continuous portions of a lithium nickel cobalt manganese oxide on a surface of the over lithiated oxide. LiaNibCocMndO2 Chemical Formula 1 where 1
US09236605B2
Provided is a positive electrode active material capable of obtaining high capacity density and also capable of obtaining sufficient charge-discharge characteristics in a region which involves high current density, when the positive electrode active material is used in a non-aqueous electrolyte secondary battery. The positive electrode active material for the non-aqueous electrolyte secondary battery includes FeF3 in which at least a part of a surface thereof is coated with an electroconductive metal oxide.
US09236601B2
To provide a lithium secondary battery which has high capacity while maintaining excellent charge-discharge characteristic, and to provide a cathode of the lithium secondary battery and a plate-like particle for cathode active material to be contained in the cathode. The plate-like particle of cathode active material for a lithium secondary battery of the present invention has a layered rock salt structure, a thickness of 5 μm or more and less than 30 μm, 2 or less of [003]/[104] which is a ratio of intensity of X-ray diffraction by the (003) plane to intensity of X-ray diffraction by the (104) plane, a mean pore size of 0.1 to 5 μm, and a voidage of 3% or more and less than 15%.
US09236597B2
A battery pack including a plurality of bare cells, a protective circuit module having a thermistor, and a case accommodating the bare cells and the protective circuit module therein is disclosed. The case may include a mounting portion having the thermistor mounted thereon and a first rib portion. The mounting portion may form a separate space between the mounting portion and the bare cells. The first rib portion may be positioned in the separate space. Accordingly, the thermistor may be guided to a particular position within the case by the first rib portion, thereby preventing damage to the thermistor.
US09236589B2
A battery module and a vehicle including a battery module. A battery module includes: a housing including an inlet to pass air from an outside of the housing into an interior of the housing; at least one rechargeable battery housed in the interior of the housing; and an opening/closing member configured to control an opening state of the inlet according to a pressure of the air acting against the opening/closing member from the outside of the housing.
US09236586B2
A battery pack including a bare cell including an electrode assembly, and a battery case including a body portion accommodating the electrode assembly, and a sealing portion extending from the body portion; and a bonding member bonding the sealing portion to the body portion, the bonding member having a slit formed therein.
US09236582B2
An OLED device includes an anode, which is transparent, anode of a sheet resistance R1, a cathode of sheet resistance R2, the ratio r=R2/R1 ranging from 0.1 to 5, a first anode contact and a second anode contact, spaced from and facing the first anode contact, and a first cathode electrical contact, which is: arranged above the active zone, offset from the first anode contact and from the second anode contact, at every point of the contact surface.
US09236578B2
The present invention relates to phosphorescent organic electroluminescent devices include at least one phosphorescent emitter and a matrix material in the emitting layer, where certain conditions must be satisfied for the positions of the triplet energy and the HOMO and LUMO.
US09236571B2
The present invention relates to polymeric materials which have electron-transporting, hole-transporting and/or emitting units in the side chains. The present invention furthermore relates to processes for the preparation of these polymers, to the use of these polymers in electroluminescent devices and to electroluminescent devices comprising these polymers.
US09236566B2
Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be utilized to improve adherence of the programmable material to the other material by inducing bonding of the programmable material to the other material, and/or by scattering the programmable material and the other material across an interface between them. The memory cells may include first electrode material, first ovonic material, second electrode material, second ovonic material and third electrode material. The various electrode materials and ovonic materials may join to one another at boundary bands having ovonic materials embedded in electrode materials and vice versa; and having damage-producing implant species embedded therein. Some embodiments include ovonic material joining dielectric material along a boundary band, with the boundary band having ovonic material embedded in dielectric material and vice versa.
US09236565B2
Embodiments of the invention provide a method for fabricating a magnetoresistive device. The method comprises: releasing a multi-layer magnetoresistive structure for forming the magnetoresistive device from a first substrate to relax an intrinsic stress in the multi-layer magnetoresistive structure such that the magnetic and/or magnetoresistive properties of the magnetoresistive device can be improved. The magnetic and/or magnetoresistive properties include, but are not limited to coercivity, squareness or abruptness of switching, magnetoresistance (MR) and resistance of the magnetoresistive device.
US09236563B2
According to one embodiment, a magnetic memory device includes a magnetoresistance effect element having a structure in which a first magnetic layer, a nonmagnetic layer, a second magnetic layer, and a third magnetic layer are stacked, wherein the third magnetic layer comprises a first region and a plurality of second regions, and each of the second regions is surrounded by the first region, has conductivity, and has a greater magnetic property than the first region.
US09236552B2
A thermoelectric micro-platform includes a suspended micro-platform, the suspended micro-platform being configured as a support layer with a device layer disposed thereon. Two arrays of series-connected thermoelectric devices are disposed partially on the micro-platform. One array is operated as Peltier coolers and the other array is operated as Seebeck sensors.
US09236548B2
A light-emitting device comprises an active-region sandwiched between an n-type layer and a p-type layer, that allows lateral carrier injection into the active-region so as to reduce heat generation in the active-region and to minimize additional forward voltage increase associated with bandgap discontinuity. In some embodiments, the active-region is a vertically displaced multiple-quantum-well (MQW) active-region. A method for fabricating the same is also provided.
US09236546B2
An optoelectronic component includes a carrier; a semiconductor chip having an active layer that generates radiation and is arranged on a carrier; a dispersed material including a matrix material and particles embedded therein arranged on the semiconductor chip and/or the carrier at least in regions, and is integral therewith; and a separating edge between the dispersed material and matrix material formed at a chip edge of the semiconductor chip.
US09236538B2
A method for making light emitting diode includes following steps. A substrate having an epitaxial growth surface is provided. A first semiconductor layer, an active layer, and a second semiconductor layer is epitaxially grown on the epitaxial growth surface of the substrate in that sequence. A cermet layer is formed on the second semiconductor layer. The substrate is removed to form an exposed surface. A first electrode is applied to cover the entire exposed surface of the first semiconductor layer. A second electrode is applied to electrically connected to the second semiconductor layer.
US09236537B2
A light-emitting diode (“LED”) device has an LED chip attached to a substrate. The terminals of the LED chip are electrically coupled to leads of the LED device. Elastomeric encapsulant within a receptacle of the LED device surrounds the LED chip. A second encapsulant is disposed within an aperture of the receptacle on the elastomeric encapsulant.
US09236534B2
A light emitting diode package, a light source module and a backlight unit including the same are provided. A plurality of light emitting diode packages are arranged on a printed circuit board without interference therebetween, by forming lines therein.
US09236532B2
The present invention relates to light-emitting diodes. A light-emitting diode according to an exemplary embodiment of the present invention includes a first group including a plurality of first light emitting cells connected in parallel to each other, and a second group including a plurality of second light emitting cells connected in parallel to each other. Each first light emitting cell and second light emitting cell has a semiconductor stack that includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. At least two light emitting cells of the first light emitting cells share the first conductivity-type semiconductor layer, and at least two light emitting cells of the second light emitting cells share the first conductivity-type semiconductor layer. The first light emitting cells are connected in series to the second light emitting cells.
US09236527B2
The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of lenses suspended in a polymer deposited or attached over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes are substantially spherical, and have a ratio of mean diameters or lengths between about 10:1 and 2:1. The diodes may be LEDs or photovoltaic diodes, and in some embodiments, have a junction formed at least partially as a hemispherical shell or cap.
US09236526B2
A light emitting structure includes lower and upper semiconductor layers having different conductive types, and an active layer disposed between the lower and upper semiconductor layers. The light emitting structure is provided on the substrate. A first electrode layer provided on the upper semiconductor layer includes a first adhesive layer and a first bonding layer overlapping each other. A reflective layer is not provided between the first adhesive layer and the first bonding layer.
US09236519B2
An embodiment of a geiger-mode avalanche photodiode includes: a body of semiconductor material, having a first surface and a second surface; a cathode region of a first type of conductivity, which extends within the body; and an anode region of a second type of conductivity, which extends within the cathode region and faces the first surface, the anode and cathode regions defining a junction. The anode region includes at least two subregions, which extend at a distance apart within the cathode region starting from the first surface, and delimit at least one gap housing a portion of the cathode region, the maximum width of the gap and the levels of doping of the two subregions and of the cathode region being such that, by biasing the junction at a breakdown voltage, a first depleted region occupies completely the portion of the cathode region within the gap.
US09236510B2
A method for making an ablated electrically insulating layer on a semiconductor substrate. A first relatively thin layer of at least an undoped glass or undoped oxide is deposited on a surface of a semiconductor substrate having n-type doping. A first relatively thin semiconductor layer having at least one substance chosen from amorphous semiconductor, nanocrystalline semiconductor, microcrystalline semiconductor, or polycrystalline semiconductor is deposited on the relatively thin layer of at least an undoped glass or undoped oxide. At least a layer of borosilicate glass or borosilicate/undoped glass stack is deposited on the relatively thin semiconductor layer. The at least borosilicate glass or borosilicate/undoped glass stack is selectively ablated with a pulsed laser, and the relatively thin semiconductor layer substantially protects the semiconductor substrate from the pulsed laser.
US09236508B2
Disclosed herein is a solid-state image pickup element, including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type.
US09236505B2
A solar cell and a method for manufacturing the same are discussed. The solar cell includes a semiconductor substrate, a first doped region of a first conductive type, a second doped region of a second conductive type opposite the first conductive type, a back passivation layer having contact holes exposing a portion of each of the first and second doped regions, a first electrode formed on the first doped region exposed through the contact holes, a second electrode formed on the second doped region exposed through the contact holes, an alignment mark formed at one surface of the semiconductor substrate, and a textured surface that is formed at a light receiving surface of the semiconductor substrate opposite the one surface of the semiconductor substrate in which the first and second doped regions are formed.
US09236504B2
A method for controlling a group of photovoltaic energy generators, the method includes providing, to a junction that is coupled to a component of a first photovoltaic energy generator (PEG), power generated by at least a second PEG such as to increase the power that is generated from the group of photovoltaic energy generators (PEGs); wherein the group of PEGs comprises the first PEG and the second PEG.
US09236503B2
A connection part for connecting an interconnector is separated from a region having a photoelectric conversion layer formed thereon to improve a strength of the connection pad, thereby provide a solar cell suppressing cracks, breaks, and the like. A solar cell includes a photoelectric conversion layer, an electrode pad formed on the photoelectric conversion layer, an interconnector connected to the electrode pad, a metal thin film formed under the photoelectric conversion layer, a relay terminal being spaced apart from the photoelectric conversion layer and the metal thin film and connected to the metal thin film by connection conductor, and a connection pad formed on the relay terminal.
US09236501B2
A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.
US09236495B2
There are provided an oxide TFT, a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the display device. The oxide thin film transistor includes: a gate electrode formed on a substrate; a gate insulating layer formed on the entire surface of the substrate including the gate electrode; an active layer pattern formed on the gate insulating layer above the gate electrode and completely overlapping the gate electrode; an etch stop layer pattern formed on the active layer pattern and the gate insulating layer; and a source electrode and a drain electrode formed on the gate insulating layer including the etch stop layer pattern and the active layer pattern and spaced apart from one another, and overlapping both sides of the etch stop layer pattern and the underlying active layer pattern.
US09236493B2
A p-type transparent oxide semiconductor includes tin oxide compounds represented by below chemical formula 1: Sn1-xMxO2 [Chemical Formula 1] wherein, in the chemical formula 1, the M is tri-valent metal and the X is a real number of 0.01˜0.05. The p-type transparent oxide semiconductor is applicable to active semiconductor devices such as TFT-LCD and transparent solar cell, due to excellent electrical and optical properties and shows superior properties in aspects of visible light transmittance (T), carrier mobility (μ) and rectification ratio as well as transparency.
US09236488B2
A thin film transistor is equipped with a silicon substrate, a channel layer, a source electrode and a drain electrode. The channel layer, the source electrode and the drain electrode are arranged on the main surface of the silicon substrate. The channel layer is composed of multiple carbon nanowall thin films, wherein the multiple carbon nanowall thin films are arranged in parallel to each other between the source electrode and the drain electrode, one end of each of the multiple carbon nanowall thin films is in contact with the source electrode, and the other end of each of the multiple carbon nanowall thin films is in contact with the drain electrode. An insulating film and a gate electrode are arranged on the rear surface side of the silicon substrate.
US09236487B2
A method of manufacturing a substrate having a thin film thereabove includes: forming a thin film above the substrate; and crystallizing at least a predetermined area of the silicon thin film into a crystallized area through relative scan of the silicon thin film which is performed while the thin film is being irradiated with a continuous wave light beam, wherein in the crystallizing, a projection of the light beam on the thin film has a major axis in a direction crossing a direction of the relative scan, and the formed crystallized area includes a strip-shaped first area extending in the direction crossing the direction of the relative scan and a second area adjacent to the strip-shaped first area, the strip-shaped first area including crystal grains having an average grain size larger than that of crystal grains in the second area.
US09236482B2
The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.
US09236476B2
Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.
US09236475B2
A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.
US09236469B2
The invention discloses a high-voltage LDMOS integrated device, which is interdigitally structured in a plan view and which including: a first area corresponding to a source fingertip area, wherein a first sectional structure of the first area particularly includes: a first drain; and a first longitudinal voltage-withstanding buffer layer located below the first drain and consisted of a first deep N-well and a first low-voltage N-well, wherein the first low-voltage N-well is located in the first deep-N well, and the first deep-N well is located in a P-type substrate; and a second area non-overlapping with the first area, wherein a second sectional structure of the second area particularly includes: a second drain; and a second longitudinal voltage-withstanding buffer layer located below the second drain and consisted of a second deep N-well and a second low-voltage N-well.
US09236467B2
Provided are methods of depositing hafnium or zirconium containing metal alloy films. Certain methods comprise sequentially exposing a substrate surface to alternating flows of an organometallic precursor and a reductant comprising M(BH4)4 to produce a metal alloy film on the substrate surface, wherein M is selected from hafnium and zirconium, and the organometallic precursor contains a metal N. Gate stacks are described comprising a copper barrier layer comprising boron, a first metal M selected from Hf and Zr, and a second metal N selected from tantalum, tungsten, copper, ruthenium, rhodium, cobalt and nickel; and a copper layer overlying the copper barrier seed layer.
US09236463B2
A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.
US09236460B2
A semiconductor device is disclosed. The semiconductor device is capable of obtaining a high reverse recovery resistant amount by allowing sheet resistance of a peripheral portion in a p type diffusion region that is in contact with a metal electrode through an insulating film on a surface to be as high as possible and reducing an increase in cost if possible. The semiconductor device includes: a p type diffusion region that is disposed in a surface layer of the one main surface of an n type semiconductor substrate; and a voltage-resistant region that surrounds the p type diffusion region.
US09236456B2
To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
US09236452B2
A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.
US09236433B2
A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type substrate and an epitaxial structure on a front-side of the N-type substrate. The epitaxial substrate includes a P-type layer adjacent to the N-type substrate and one or more additional SiC layers on the P-type layer opposite the N-type substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type substrate.
US09236417B2
A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type.
US09236416B2
A memory cell with a substrate; a first transistor comprising a first gate width and a terminal; resistive memory elements above the transistor, each element comprising an element width, a first and second end; parallel conductive lines above the first memory elements and coupled to the first elements at their first ends; a second plurality of resistive memory elements disposed above the conductive lines, each element comprising the width, the first end, and the second end and coupled to the conductive lines at their first ends; a second transistor disposed above the second plurality of resistive memory elements and comprising a gate width and a terminal, the first memory elements is jointly coupled to the terminal of the first transistor at their second ends; the second memory elements is jointly coupled to the terminal of the second transistor at their second ends; and the gate width is larger than the element width.
US09236413B2
A color filter 5 is formed above a semiconductor substrate SB, in an area above a predetermined light receiving portion among a plurality of light receiving portions 1. A sacrificial layer 8 is formed on upper and side of the first color filter 5. Color filters 6 and 7 are formed above the semiconductor substrate SB, in areas above other light receiving portions adjacent to the predetermined light receiving portion, to expose at least part of the upper surface area of the first color filter 5 on the sacrificial layer 8. The sacrificial layer 8 is etched to remove the upper and side areas of the color filter 5 on the sacrificial layer 8 to form hollow portions 9 between the color filter 5 and the color filter 6 and between the color filter 5 and the color filter 7.
US09236410B2
In a solid-state image pickup device including a pixel that includes a photoelectric conversion portion, a carrier holding portion, and a plurality of transistors, the solid-state image pickup device further includes a first insulating film disposed over the photoelectric conversion portion, the carrier holding portion, and the plurality of transistors, a conductor disposed in an opening of the first insulating film and positioned to be connected to a source or a drain of one or more of the plurality of transistors, and a light shielding film disposed in an opening or a recess of the first insulating film and positioned above the carrier holding portion.
US09236404B2
An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
US09236402B2
A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/μm. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.
US09236401B2
A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.
US09236399B1
A liquid crystal display device includes a gate electrode; a gate insulating layer on the gate electrode; an active layer on the gate insulating layer corresponding to the gate electrode; source and drain electrodes on the active layer; a first passivation layer on the source and drain electrodes; a common electrode on the first passivation layer; a second passivation layer on the common electrode, covering the common electrode, and having a separate region from the first passivation layer at a thickness of the common electrode; a pixel electrode on the second passivation layer and connected to the drain electrode through a drain contact hole; and a common line at a same layer as the pixel electrode and connected to the common electrode.
US09236396B1
A monolithic three dimensional NAND string includes a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The NAND string also includes a memory film located between the semiconductor channel and the plurality of control gate electrodes and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. The NAND string also includes a plurality of discrete cover silicon oxide segments located between the memory film and each respective clam-shaped portion of the blocking dielectric containing a respective control gate electrode. Each of the plurality of cover silicon oxide segments has curved upper and lower sides and substantially straight vertical sidewalls.
US09236395B1
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
US09236390B2
A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.
US09236376B2
There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000.
US09236365B2
Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.
US09236363B2
A semiconductor device includes a substrate, first and second bond pad structures supported by the substrate and spaced from one another by a gap, and a wire bond foot jumper extending across the gap and bonded to the first and second bond pad structures.
US09236358B2
An integrated circuit package comprising a substrate and at least one semiconductor die is described. A connection unit may provide electrical connections between the substrate and the semiconductor die. The connection unit may comprise a stack of conduction layers and isolation layers stacked atop each other. The stack may include a microstrip line or a coplanar waveguide. The microstrip line or the coplanar waveguide may be part of a balun, a power divider, or a directional coupler.
US09236356B2
A semiconductor package includes a substrate, a grounding layer, a chip, a package body, and a shielding layer. The substrate includes a lateral surface and a bottom surface. The grounding layer is buried in the substrate and extends horizontally in the substrate. The chip is arranged on the substrate. The package body envelops the chip and includes a lateral surface. The shielding layer covers the lateral surface of the package body and the lateral surface of the substrate, and is electrically connected to the grounding layer, where a bottom surface of the shielding layer is separated from a bottom surface of the substrate.
US09236353B2
An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.
US09236347B2
Manufacturing a DC-DC converter on a chip includes: providing a die having a p-type top side and an n-type bottom side; removing an interior portion, creating a hole; flipping the interior portion; inserting the interior portion into the hole; fabricating high-side switch cells in the interior portion's top side and low-side switch cells in the exterior portion's top side; sputtering a magnetic material on the entire top side; burrowing tunnels into the magnetic material; and applying conductive material on the magnetic material and within the tunnels, electrically coupling pairs of high-side and low-side switches, with each pair forming a micro-power-switching phase, where the conductive material forms an output node of the phase, and the conductive material in the burrowed tunnels forms, in each phase, a torodial inductor with a single loop coil and, for the plurality of phases, a directly coupled inductor.
US09236340B2
A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines. First and second vertical patterns vertically cross the first and second selection lines. The first and second vertical patterns are connected in common to the upper line. Each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other. The first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively.
US09236334B2
A wiring substrate includes a wiring layer, an outermost insulating layer laminated to the wiring layer, and a pad electrically connected to the wiring layer and exposed from a surface of the outermost insulating layer. The pad consists essentially of a first metal layer and a second metal layer. The first metal layer includes a first surface, which is exposed from the surface of the outermost insulating layer, and a second surface, which is located opposite to the first surface. The second metal layer includes is formed between the second surface of the first metal layer and the wiring layer. The first metal layer is formed from a metal selected from gold or silver or from an alloy including at least one of gold and silver. The second metal layer is formed from palladium or a palladium alloy.
US09236327B2
A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines.
US09236324B2
An electric power semiconductor device includes a power module and a heat dissipating member connected to the power module through a heat-conductive insulating resin sheet in which a mold resin part included in the power module has a protruding part in its peripheral part to prevent the heat-conductive insulating resin sheet from expanding in a planar direction. The heat-conductive insulating resin sheet is slightly thicker than the protruding part and has a resin exuding part exuded from a small gap between the protruding part and the heat dissipating member while the power module and the heat dissipating member are heated and pressurized to be bonded.
US09236321B2
A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing.A semiconductor device has a structure formed by covering a principal surface of a semiconductor chip having the principal surface and a plurality of MIS type FETs formed over the principal surface with a plurality of metal plate wires having pectinate shapes; allocating the pectinate parts alternately in a planar view over the principal surface; and further electrically coupling the plural metal plate wires to a plurality of terminals.
US09236318B1
A glass composition for protecting a semiconductor junction is made of fine glass particles prepared from a material in a molten state obtained by melting a glass raw material which contains at least ZnO, SiO2, B2O3, Al2O3 and at least two oxides of alkaline earth metals selected from a group consisting of BaO, CaO and MgO and substantially contains none of Pb, As, Sb, Li, Na and K, the glass composition for protecting a semiconductor junction containing no filler.
US09236311B2
A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.
US09236310B2
In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.
US09236309B2
Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride.
US09236307B2
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.
US09236306B2
A method for manufacturing a semiconductor device according to this specification solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The method is applicable to a BCD process and the like.
US09236298B2
An electronic device includes an interlevel dielectric layer formed over a substrate and has a first set of openings and a second set of openings formed through the interlevel dielectric layer. The substrate includes conductive areas. A conductive contact structure is formed in the first set of openings in the interlevel dielectric layer to make electrical contact with the conductive areas of the substrate. A functional component is formed in the second set of openings in the interlevel dielectric layer and occupies a same level as the conductive contact structure.
US09236296B2
Various embodiments provide an MIM capacitor and fabrication method thereof. An exemplary MIM capacitor can include a dielectric layer disposed over a substrate containing a conductive layer. The dielectric layer can include a groove to expose the conductive layer in the substrate. A first metal layer can be disposed on a bottom surface and a bottom portion of a sidewall surface of the groove. A top surface of the first metal layer on the sidewall surface of the groove can be lower than a top surface of the dielectric layer. A dielectric material layer can be disposed on the first metal layer and on a top portion of the sidewall surface of the groove. A second metal layer can be disposed on the dielectric material layer; and a third metal layer can be disposed on the second metal layer to fill the groove.
US09236295B2
Provided is a semiconductor apparatus in which a plurality of semiconductor chips stacked in a vertical direction. Each of the semiconductor chips comprises: a bank area comprising a plurality of banks configured to store data; and a peripheral area including a pad area in which a plurality of pads configured to receive signals for controlling the bank area and a plurality of TSV for electrically connecting the plurality of pads, respectively.
US09236290B2
A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.
US09236283B2
A chamber apparatus including a chamber which accommodates a substrate having a coating film formed thereon; a first heating part which is accommodated in the chamber and disposed on a first face side of the substrate; a second heating part which is accommodated in the chamber and disposed on a second face side of the substrate opposite to the first face; and a pressure control part which is capable of pressurizing and depressurizing inside of the chamber in a heated state.
US09236280B2
Disclosed is a substrate processing apparatus including a processing vessel in which a target substrate W is processed by using a high-pressure fluid in a supercritical state or a subcritical state, and pipes that are divided into a first pipe member and a second pipe member in a flowing direction of the fluid and circulate the fluid are connected to processing vessel. A connecting/disconnecting mechanism moves at least one of first and second pipe members between a connection position and a separation position of first pipe member and the second pipe member, and opening/closing valves are installed in each of first and second pipe members and are closed at the time of separating pipe members.
US09236276B2
In a manufacturing method of a semiconductor device, a semiconductor chip is sealed with a resin, and then a laser is applied to remove the resin so that a part of the semiconductor chip is exposed. The semiconductor chip is made of a material that has a lower absorptivity of the laser than the resin and is not melted by the laser. The laser has a wavelength that passes through the semiconductor chip and has a lower absorptivity in the semiconductor chip than in the resin. The laser is applied to the resin from a side adjacent to one of plate surfaces of the semiconductor chip, so that the resin sealing the one of the plate surfaces is sublimated and removed and at least a part of the resin sealing the other of the plate surfaces is subsequently sublimated and removed by the laser having passed through the semiconductor chip.
US09236262B2
A substrate of SOI type is covered by an etching mask defining three distinct semiconductor patterns. A lateral spacer is formed around the three patterns and performs the connection between two adjacent patterns. The buried insulating layer is eliminated so as to define a cavity which suspends a part of a first pattern. The first etching mask is eliminated. A gate dielectric is formed on two opposite main surfaces of the first pattern. The resist is deposited in the cavity and on the first pattern and is then exposed to form two patterns defining the bottom and top gates. An electrically conducting material is deposited in the cavity and on the first pattern so as to form the bottom gate and the top gate on each side of the first semiconductor material pattern.
US09236258B2
One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.
US09236251B2
Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.
US09236248B2
A (000-1) C-plane of an n− type silicon carbide substrate having an off-angle θ in a <11-20> direction is defined as a principal plane, and a periphery of a portion of this principal surface layer defined as an alignment mark is selectively removed to leave the convex-shaped alignment mark. The alignment mark has a cross-like plane shape such that two rectangles having longitudinal dimensions tilted by 45 degrees relative to the <11-20> direction are orthogonal to each other. When a film thickness of a p− type epitaxial layer is Y; a width of the alignment mark parallel to the principal surface of the n− type silicon carbide substrate is X; and an off-angle of the n− type silicon carbide substrate is θ, an epitaxial layer is formed on an upper surface of the alignment mark such that Y≧X·tan θ is satisfied.
US09236245B2
Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.
US09236240B2
A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width WT defined by outer and inner rings of the protection unit. The substrate is etched to form at least a trench in the second region of the substrate. The WT of the protection unit is sufficiently wide to protect the first region of the wafer substrate such that the first region is devoid of trench.
US09236237B2
Instead of sealing together the upper and lower panels of a display device with only a solid-filled sealing material, a vacuum region is provided in suction-force-applying communication with at least one of the panels and anchored to the other so as to pull the panels together due to pressure difference with and ambient atmosphere. The display device includes: a vacuum region defined by a pair of spaced apart, resilient and gas impermeable support barriers formed to integrally extend from at least one of the upper and lower panels of the display device and having the other end in vacuum region closing contact with the other display panel where the vacuum region is positioned in a peripheral area of the display device.
US09236235B2
An ion guide includes a plurality of curved electrodes and an ion deflecting device. The electrodes are arranged in parallel with each other and with a central curved axis, the curved central axis being co-extensive with an arc of a circular section having a radius of curvature, each electrode being radially spaced from the curved central axis, wherein the plurality of electrodes define a curved ion guide region arranged about the curved central axis and between opposing pairs of the electrodes. The ion deflecting device may include a device for applying a DC electric field to two or more of the electrodes in a radial direction. The ion deflecting device may include a pair of curved, parallel ion deflecting electrodes, which are in addition to curved electrodes utilized for applying an RF ion guiding field.
US09236228B2
Methods for processing a substrate in a plasma processing chamber employing a plurality of RF power supplies. The method includes pulsing at a first pulsing frequency a first RF power supply to deliver a first RF signal between a high power state and a low power state. The method further includes switching the RF frequency of a second RF signal output by a second RF power supply between a first predefined RF frequency and a second RF frequency responsive to values of a measurable chamber parameter. The first RF frequency and the second RF frequencies and the thresholds for switching were learned in advance during a learning phase while the first RF signal pulses between the high power state and low power state at a second RF frequency lower than the first RF frequency and while the second RF power supply operates in different modes.
US09236227B2
An inhalable cold plasma mask device for generation of a breathable cold plasma for delivery to a patient. A biocompatible gas is received in a dielectric barrier discharge (DBD) device that is energized by an electrode that receives energy from a pulsed source. The DBD device can be grounded by a grounding structure. A grounding screen can be used prior to inhalation of the cold plasma. The inhalable cold plasma mask device includes the use of a single-layer or a two-layer approach to its construction. The inhalable cold plasma mask device can have one or two DBD devices. Such a device and associated method can be used to treat upper respiratory tract infections, as well as reducing inflammation, sinus and esophageal polyps in both size and frequency of occurrence.
US09236220B2
An automatic setting method of an observation condition to facilitate analysis of an image and a sample observation method by automatic setting in an observation method of a structure of a sample by the electronic microscope and an electronic microscope having an automatic setting function are provided. The method includes a step of irradiating a fixed position in an observation region with an intermittent pulsed electron beam; a step of detecting a time change of an emission electron from the sample by the intermittent electron beam; and a step of setting the observation condition of the electronic microscope from the time change of the emission electron.
US09236204B2
A keyswitch structure includes a base, a keycap, at least one lift mechanism, a link, and a restoration mechanism. The lift mechanism is connected to and between the base and the keycap. The link is moveably on the base. The restoration mechanism is disposed on the link and the base and can generate a restoration force. When the keycap is pressed down by a user to move toward the base, a sliding portion of the lift mechanism slides on the base to drive the link to move relative to the base. Further, when the pressing on the keycap by the user is eliminated, the restoration force urges the link to move to drive the sliding portion to slide reversely, so that the keycap moves away from the base.
US09236196B2
The electric double-layer capacitor of the present invention comprises an electrolyte solution comprising γ-butyrolactone as the solvent and a coated electrode. The coated electrode is produced by using water as the solvent, and prepared by coating a slurry onto a current collector, wherein the slurry consists of an electrode material which is the solute, an electrically conductive auxiliary agent, and an elastomer having an expansion rate of 50% or less in γ-butyrolactone at 85° C. after 100 hours as the binding agent. For example, a styrene-butadiene elastomer is employed as the elastomer. Because expansion rate in γ-butyrolactone is low, deterioration of internal resistance does not occur. Styrene-butadiene elastomer is easy to handle since water can be used as the solvent for the slurry.
US09236189B2
A direct current (DC) link capacitor module includes a printed circuit board (PCB) formed by sequentially disposing a first electrode substrate, an insulation substrate, a second electrode substrate, a third electrode substrate; a plurality of DC link capacitors connected in parallel to each of the first electrode substrate and the second electrode substrate; a plurality of first Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the DC link capacitors; and a plurality of second Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the first Y-capacitors, thereby achieving a miniaturization and facilitating a fabrication by connecting the plurality of DC link capacitors using the PCB.
US09236187B2
A multilayer ceramic capacitor includes a ceramic main body including an inner layer portion including third ceramic layers and a plurality of inner electrodes arranged at interfaces between the third ceramic layers, and first and second outer layer portions respectively including first and second ceramic layers, the first and second ceramic layers being arranged vertically so as to sandwich the inner layer portion. The third ceramic layers and the first and second outer layer portions contain a perovskite-type compound represented by ABO3 where A contains one or more of Ba, Sr, and Ca, B contains one or more of Ti, Zr, and Hf, and O represents oxygen) as a main component. Where a rare-earth element concentration (CR) in the third ceramic layers is compared to a rare-earth element concentration (Cr) in outermost layer portions including at least outermost surfaces of the first and second outer layer portions, CR>Cr (inclusive of Cr=0).
US09236183B2
A capacitor having a dielectric consisting of a glass layer with an alkali metal oxide content of at most 2 wt % and a thickness of at most 50 μm is provided. The capacitor includes at least two metal layers which are separated by the glass layer. The glass layer is preferably produced by a down-draw method or by an overflow down-draw fusion method.
US09236179B1
An interconnectable bobbin has first and second end flanges and a fastener on the first end flange positioned to engage a second bobbin on an adjacent leg of a multiple leg magnetic core. A magnetic component apparatus includes one or more of the interconnectable bobbins, the magnetic component apparatus including a magnetic core with first and second legs, the first leg extending into a first bobbin, and the second leg extending into a second bobbin, wherein the first and second bobbins are fastened together.
US09236176B2
A device for generating a magnetic field includes at least one electric coil having electric conductors that are arranged along a circular arc within a first angular range and that deviate from the circular arc within a second angular range. At least one magnetic yoke is arranged along a part of the first angular range.
US09236172B2
A conductor pattern of a coil part formed in a spiral shape on a magnetic substrate, which includes: a primary conductor pattern; and a secondary conductor pattern formed on the primary conductor pattern. The primary conductor pattern is formed to have a longitudinal section including a first horizontal portion and a first vertical portion electrically connected to an end portion of one surface of the first horizontal portion. The secondary conductor pattern is formed to have a longitudinal section including a second horizontal portion corresponding to the first horizontal portion and a second vertical portion electrically connected to an end portion of one surface of the second horizontal portion.
US09236171B2
A coil component includes: an insulating resin layer provided between a first planar spiral conductor formed on a back surface of a first substrate and a second planer spiral conductor formed on a back surface of a second substrate; an upper core covering a third second planer spiral conductor formed on a front surface of the first substrate on which the insulating resin layer is formed; and a lower core covering a fourth planer spiral conductor formed on a front surface of the second substrate on which the insulating resin layer is formed. One of the upper and lower cores is formed of a metal-magnetic-powder-containing resin. The coil component includes connecting portions disposed respectively at center and outside portions of each of the first and second substrates so as to physically connect the upper and lower cores.
US09236169B2
Provided is an electromagnetic wave shielding structure, including: a substrate; and a porous composite film formed on the substrate, wherein the porous composite film includes a continuous phase network fused from a plurality of metal nanoparticles, a first resin composition coated on a surface of the continuous phase network and a plurality of holes which are void spaces in the continuous phase network coated with the first resin composition.
US09236158B2
A main object of the present invention is to provide a practical slurry having a polar solvent as the dispersion medium for a sulfide solid electrolyte material. The present invention solves the above-mentioned problem by providing a slurry having: a sulfide solid electrolyte material, and a dispersion medium having at least one selected from the group consisting of tertiary amine; ether; thiol; ester having a functional group of a 3 or more carbon number bonded with a carbon atom of an ester bonding and a functional group of a 4 or more carbon number bonded with an oxygen atom of the ester bonding; and ester having a benzene ring bonded with a carbon atom of an ester bonding.
US09236147B1
An instruction to read at least a portion of a superblock is received where the superblock is stored on at least a first solid state storage die. It is determined if adjusted threshold information, associated with the first solid state storage die and the superblock, is stored. If it is determined that adjusted threshold information is not stored, then an adjusted threshold is determined and a read is performed on the first solid state storage die using the determined adjusted threshold. If it is determined that adjusted threshold information is stored, then a read is performed on the first solid state storage die using the stored adjusted threshold information.
US09236143B2
A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold programming values for the generic programmable address scrambler.
US09236139B1
Reducing peak current and/or power consumption during verify of a non-volatile memory is disclosed. During a program verify, only memory cells in a first physical segment of the selected word line are verified during an initial program loop; memory cells in a different physical segment of the word line are locked out and not verified. The locked out memory cells may be slower to program. During a later program loop, memory cells in all physical segments are program verified. Locked out strings do not conduct a significant current during verify, thus reducing current/power consumption.
US09236135B2
According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell, a voltage generator configured to output a first voltage and a second voltage, and a controller. The controller executes a write operation, which includes a first read operation, a program operation, and a verify operation. The controller executes the first read operation before the program operation and the verify operation. The controller executes the first read operation by applying the first voltage to a gate of the memory cell. The controller executes an erase verify operation by applying the second voltage to the gate of the memory cell. The first voltage is higher than the second voltage.
US09236131B1
In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit may occur when charges which are accumulated in select gate lines due to plasma etching, discharge through a remaining portion of the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates that the bias has exceed a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit.
US09236130B2
Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of strings, wherein each of the plurality of strings includes a first memory cell group, and a second memory cell group and peripheral circuits configured to generate a first precharge voltage applied to the first memory cell group and a second precharge voltage applied to the second memory cell group when a channel precharge operation is performed during a program operation, and generate a program voltage to apply the program voltage to the memory cell array when a program voltage application is performed.
US09236129B2
Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory.
US09236123B2
A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that establishes an electrical resistance that changes in response to an application of a write voltage after a forming voltage has been applied, the first memory cell to which the forming voltage is applied, and the second memory cell to which the forming voltage is not applied, and the second memory cell being configured to store one of first and second logic values constituting first information, the first and second logic values being different from each other.
US09236121B2
A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.
US09236114B2
In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an NMOS transistor coupled between a power node and the bit line. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line. The noise threshold control circuit is connected to the sense amplifier output and the bit line. The noise threshold control circuit comprises an inverter.
US09236110B2
A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
US09236103B2
A magnetic device includes a magnetized polarizing layer, a free magnetic layer, and a reference layer. The free magnetic layer forms a first electrode and is separated from the magnetized polarizing layer by a first non-magnetic metal layer. The free magnetic layer has a magnetization vector having a first and second stable state. The reference layer forms a second electrode and is separated from the free-magnetic layer by a second non-magnetic layer. Unipolar current is sourced through the polarizing, free magnetic and reference layers. Switching of the magnetization vector of the free magnetic layer from the first stable state to the second state is initiated by application of a first unipolar current pulse, and switching of the magnetization vector of the free magnetic layer from the second stable state to the first stable state is initiated by application of a second unipolar current pulse.
US09236089B2
An information processing apparatus comprising that includes a reproduction unit to reproduce video content comprising a plurality of frames; a memory to store a table including object identification information identifying an object image, and frame identification information identifying a frame of the plurality of frames that includes the object image; and a processor to extract the frame including the object image from the video content and generate display data of a reduced image corresponding to the frame for display.
US09236088B2
An external application is loaded by an electronic device. The external application loads one or more internal applications. The internal application loads a player application, such as a video player. At least one communication channel is configured between the external application and the player application. Subsequently, the player application may provide signals to the external application via the communication connection when one or more events occur. In response, the external application may perform one or more actions and/or may provide reply signals to the player application. Additionally, the player application may provide instructions to the external application and/or the external application may provide instructions to the player application.
US09236085B1
A disk drive including a disk storing a defect log including one or more defect records, wherein each of the defect records spans multiple words and comprises chunks which are word aligned, each chunk comprising one or more record fields, and a controller configured to read the defect records on a word basis. A method for performing a defect process on the disk drive including selecting a defect record from the defect log, selecting record fields in the selected defect record, reading the selected defect record on a word basis, and searching the selected record fields which are located in a same chunk of the selected record at a same time to determine when the selected defect record matches a target defect record.
US09236084B1
According to one embodiment, a system for processing data includes a controller configured to: receive data read from a magnetic storage medium, apply a finite impulse response (FIR) filter to the data to obtain equalized data, and direct the equalized data through either a first FIR gain module or a second FIR gain module to control FIR gain of the equalized data, wherein the first FIR gain module is utilized when reading data in an asynchronous mode, and wherein the second FIR gain module is utilized when reading data in a synchronous mode and a FIR gain value of the second FIR gain module is automatically controlled. Other systems and methods for processing data using dynamic gain control with adaptive equalizers are presented according to more embodiments.
US09236077B2
According to one aspect of the present invention, provided is glass for use in substrate for information recording medium, which comprises, denoted as molar percentages, a total of 70 to 85 percent of SiO2 and Al2O3, where SiO2 content is equal to or greater than 50 percent and Al2O3 content is equal to or greater than 3 percent; a total of equal to or greater than 10 percent of Li2O, Na2O and K2O; a total of 1 to 6 percent of CaO and MgO, where CaO content is greater than MgO content; a total of greater than 0 percent but equal to or lower than 4 percent of ZrO2, HfO2, Nb2O5, Ta2O5, La2O3 Y2O3 and TiO2; with the molar ratio of the total content of Li2O, Na2O and K2O to the total content of SiO2, Al2O3, ZrO2, HfO2, Nb2O5, Ta2O5, La2O3, Y2O3 and TiO2 ((Li2O+Na2O+K2O)/(SiO2+Al2O3+ZrO2+HfO2+Nb2O5+Ta2O5+La2O3+Y2O3+TiO2)) being equal to or less than 0.28. Further provided are the substrate for information recording medium, information recording medium and their manufacturing methods according to the present invention.
US09236073B1
Systems and methods are disclosed having a write fault threshold for a set of tracks. A set of tracks may have a shared write fault threshold budget, and a write fault threshold for the second track may be selected based on the shared budget reduced by an off-track position error signal value of the first track. In certain embodiments, an apparatus may comprise a processor configured to determine a position error signal value for a first data track, set a write fault threshold for a second data track adjacent to the first data track based on the position error signal, and write data to the second data track based on the write fault threshold.
US09236064B2
The subject disclosure is directed towards dynamically computing anti-aliasing filter coefficients for sample rate conversion in digital audio. In one aspect, for each input-to-output sampling rate ratio (pitch) obtained, anti-aliasing filter coefficients are interpolated based upon the pitch (e.g., using the fractional part of the ratio) from two filters (coefficient sets) selected based upon the pitch (e.g., using the integer part of the ratio). The interpolation provides for fine-grained cutoff frequencies, and by re-computation for each pitch, smooth anti-aliasing with dynamically changing ratios.
US09236051B2
Systems and methods for bio-phonetic multi-phrase speaker identity verification are disclosed. Generally, a speaker identity verification engine generates a dynamic phrase including at least one dynamically-generated word. The speaker identity verification engine prompts a user to speak the dynamic phrase and receives a dynamic phrase utterance. The speaker identity verification engine extracts at least one voice characteristic from the dynamic phrase utterance and compares the at least one voice characteristic with a voice profile the generate a score. The speaker identity verification engine then determines whether to accept a speaker identity claim based on the score.
US09236044B2
A speech synthesis system can record concatenation costs of most common acoustic unit sequential pairs to a concatenation cost database for speech synthesis by synthesizing speech from a text, identifying a most common acoustic unit sequential pair in the speech, assigning a concatenation cost to the most common acoustic sequential pair, and recording the concatenation cost of the most common acoustic sequential pair to a concatenation cost database.
US09236042B2
A vibration member (140) has a sheet shape. A piezoelectric element (130) is attached to one surface of the vibration member (140). A support member (110) supports the edge of the vibration member (140). The support member (110) includes a first facing portion (112) and a second facing portion (114). The first facing portion (112) faces the surface of the vibration member (140) to which the piezoelectric element (130) is attached. The second facing portion (114) faces the surface of the vibration member (140) which is located on the opposite side to the piezoelectric element (130). A first spring (152) is provided between the first facing portion (112) and the vibration member (140) or the piezoelectric element (130). A second spring (154) is provided between the second facing portion (114) and the vibration member (140).
US09236039B2
Technologies are generally described for a virtual instrument playing system. In some examples, a virtual instrument playing system may include a sensor data receiving unit configured to receive first sensor data of a first user and second sensor data of the first user, a sound event prediction unit configured to detect a sound event of the first user and to predict a sound generation timing corresponding to the sound event of the first user based at least in part on the first sensor data of the first user, an instrument identification unit configured to identify a virtual instrument corresponding to the sound event from one or more virtual instruments based at least in part on the second sensor data of the first user, a sound data generation unit configured to generate sound data of the first user regarding the identified virtual instrument based at least in part on the sound generation timing, and a video data generation unit configured to generate video data of the first user regarding the identified virtual instrument based at least in part on the second sensor data of the first user.
US09236027B2
The present invention provides a display system capable of efficiently calibrating image content even when the image is displayed and thereby capable of reducing the time and cost required for calibration, and also provides a computer-readable recording medium. The control device thereof processes an image to be displayed on a display section beforehand so as to be usable for calibration. While the image is actually being displayed on the display section, the control device captures an image displayed on the display section using a capturing device at the timing at which a calibration image is displayed, compares the luminance or color in the calibration image with the luminance or color in the image obtained by capturing the calibration image, and creates correction information for correcting an image signal to be output to the display section on the basis of the result of the comparison.
US09236022B2
According to one aspect of the present invention, the provided is a gate driving circuit, comprising: a first switch control circuit, being configured to be respectively coupled to each of the multiple stages of shift register units; a second switch control circuit, being configured to be respectively coupled to each of the multiple stages of shift register units. The first switch control circuit controls the multiple stages of shift register units to turn on in a forward sequence; the second switch control circuit controls the multiple stages of shift register units to turn on in a backward sequence.
US09236020B2
A display device includes a display panel and a lens plate covering the display panel. The display panel includes pixel units, and each pixel unit includes a first pixel portion and a second pixel portion. The first pixel portion includes a first switch and a slit indium tin oxide (ITO) connected to the first switch. The second pixel portion includes a second switch and a full ITO connected to the second switch.
US09236019B2
A display device includes multiple pixels, a gate driver and a data driver. Each pixel includes a transistor and a pixel capacitor electrically coupled to the transistor. The gate driver is configured to turn on the transistor of a first pixel for one time during a first turn-on period of multiple turn-on cycles of a frame cycle of a frame displayed by the display device. The data driver is configured to charge the pixel capacitor of the first pixel via the transistor of the first pixel to a first over-charge voltage and a data voltage during an over-charge period and a recovery period of the first turn-on period. The first over-charge voltage is different from the data voltage. A method for driving the display device is also provided.
US09236009B2
An organic light emitting display device includes: a display panel; a timing controller configured to receive image data when a vertical sync signal is activated, to receive reference data corresponding to the image data when the vertical sync signal is deactivated, and to generate an emission control signal in accordance with emission duty information of the reference data; and an emission driver configured to supply first and second emission powers to the display panel, and to control a duration of a period during which a potential difference between the first and second emission powers is greater than or equal to a reference value in accordance with the emission control signal.
US09236005B2
A counter 102 counts the accumulated lighting time or the accumulated lighting time and the intensity of lighting of each pixel by a first image signal 101A and stores them in a volatile memory 103 or a nonvolatile memory 104. A correction circuit 105 corrects the first image signal based on the correction data stored previously in a correction data storage section 106 in accordance with the degree of the degradation of each spontaneous light emitting element by the use of the accumulated lighting time or the accumulated lighting time and the intensity of lighting, and produces a second image signal 101B. By the second image signal 101B, a display unit 107 can provide a uniform screen having no variation in luminance even if the light emitting elements in a part of the pixels are degraded.
US09236003B2
A user terminal apparatus is disclosed. A user terminal apparatus according to various exemplary embodiments includes a communication unit which communicates with an external apparatus, an image sensor unit which photographs an image being displayed on the display apparatus at a photographing speed above a frame rate of the display apparatus, and a control unit which controls to identify pattern information based on a placement of a pattern frame included in the image photographed by the image sensor unit, and to receive data related to the display apparatus from the external apparatus based on the identified pattern information.
US09236001B2
A driving method of an electro-optic device is capable of sufficiently providing a threshold voltage compensation time of a driving transistor and a data writing time. A driving method of an electro-optic device including a first power source, a second power source, data lines, scan lines, signal lines, and pixel circuits, includes: a first step in which a light emitting element is in a non-light-emitting state, and a second transistor is turned on by a change of a pulse applied to a signal line; and a second step in which the scan line is sequentially and exclusively selected after the second transistor is turned on, a third transistor including a gate connected to a selected scan line is turned on, and a corresponding data voltage is written to a first node from the data line through the third transistor.
US09235997B2
Provided is an image display panel, image display panel installation equipment, and a manufacturing method for an image display panel, which display an image by using reflective light and realize a high reproducibility of a base image with a simple method. An image is displayed by a plate-like body processed through carving work. The plate-like body has a main portion made of a metal reflecting light and a surface layer portion made of a material absorbing light more than the main portion. The carving work forms linear V-shaped grooves on the front surface side of the plate-like body such that each minute section includes a plurality of grooves. Shading of the image is expressed by the depths of the V-shaped grooves. The image is displayed by light absorption on the surface layer portion and light reflection on the V-shaped grooves.
US09235984B2
A remote control device includes first and second pointing devices, wherein each pointing device is provided in a different plane, for the provision of flexible and ergonomic user commands. The first pointing device may be provided on an upper surface of a remote control housing (in a first plane) while the second pointing device may be provided on a lower surface of the remote control housing (in a second plane). In this configuration, a user's thumb may engage the first pointing device which the user's finger engages the second pointing device. Combinations of thumb and finger movement are detected through the pointing devices and interpreted to generate remote control signals.
US09235983B2
Apparatus and methods for, among other things, a group-based reactive service discovery protocol are discussed. In an example, a method can include broadcasting a first group beacon at a group interval using a first station belonging to a first group of stations and broadcasting a service request to the second group during a query interval of the second group. In an example, the first group beacon can include a service update alert configured to alert other members of the first group of an anticipated service request and response event to learn services available from a second group. In an example, the service update alert can include a beginning time for the anticipated service request and response event.
US09235982B2
Alert conditions datasets are created from historic data taken from actual incidents for which the alert condition datasets are to indicate during future operations. A networked computers system including various devices is monitored for alert conditions associated with one, or more, of the devices. The severity of an alert is based on the number of alert conditions met for a given alert conditions dataset.
US09235976B2
A particular smart hazard detector may itself function as a guide during a process of installation of the same at an installation location. Additionally, the installation location of the particular smart hazard detector may play a central role in how various settings of the smart hazard detector are defined and adjusted over time.
US09235963B2
A video poker machine configured to allow a player to play a card game includes at least one display device, at least one input device, and at least one computer configured to display at least a first hand and a second hand of at least five cards all face up, each hand including the same five cards. A player is provided an option to play a hand by selecting none, one or more than one of the face up cards from the first hand and the second hand and any additional hands as cards to be held. Each of the cards not selected to be held are discarded from each hand and replaced with a face up card. The player is provided a pre-established amount based on the amount of a wager made on the hand if the resulting cards of the hand comprise a predetermined poker hand ranking.
US09235958B2
An apparatus and method allow a value of a credit balance on a gaming device to be determined. If the value is not less than a predetermined threshold, a benefit is provided to the player of the gaming device. In various embodiments, the benefit may be, e.g., an increase in the player's credit balance.
US09235954B2
Methods, computer readable media and systems related to wagering games, and in particular those that concern providing and redeeming partial game outcomes. One example method includes receiving a completion request from a player who is operating a gaming device to complete at least one partial game outcome. The partial game outcome was previously provided to the player, who used a first device that is different than the gaming device. This example method includes determining that the player is entitled to a complete game outcome, displaying the partial game outcome on the gaming device, determining the complete game outcome, and then displaying the complete game outcome.
US09235949B2
Systems and methods which allow for the self-service selection and recording of local storage devices which can be provided as part of a larger object such as a toy. Specifically, the systems and methods discussed herein generally comprise self-service kiosks or other related systems whereby a final consumer, who is engaged in the manufacture or creation of a personalized or semi-personalized toy, can provide for transfer of sound or other data to a local storage device which will be incorporated into the toy in an on-demand fashion.
US09235938B2
A wireless equipment management system that is configured to track sensors for work measurement for predetermined events. The sensors are configured to measure event durations of a specific piece of equipment as defined by a user and sent to a Network Management Center. This enables the user to measure work times by configuring work events as sensor input events. The event durations can be displayed and reports can be produced at the Network Management Center.
US09235937B1
A satellite sensor system includes a base unit and a packaged motion sensor configured to be removably couplable to the base unit. The base unit is configured to mount to a vehicle and to faithfully transmit vehicle motion to an attached sensor.
US09235936B2
A base unit installed in a vehicle including a vehicle communication module for communicating with a controller, the controller monitoring at least one operating parameter of the vehicle. The base unit also includes a transceiver and a processor configured to receive the at least one operating parameter of the vehicle from the vehicle communication module and process the at least one operating parameter to detect an event, wherein the event is used for driver compliance logging. The transceiver is configured to transmit the event to at least one external device.
US09235934B2
A wearable article, such as glasses for a virtual reality program or glasses for an augmented reality application, using light sources and a photodetector that detects their light and outputs data indicative of the detected light. The wearable article uses one or more controllers to determine its position and/or orientation in the environment based on the data output by the photodetector. Data from one or more auxiliary motion sensing devices, e.g., a relative motion sensor such as an inertial device or other auxiliary motion device relying on acoustics, optics or electromagnetic waves within or outside the visible spectrum, can be used to supplement the position and/or orientation data from the photodetector.
US09235930B2
A method for generating a just noticeable depth difference (JNDD) model including controlling a real size of an object to maintain a perceived size of the object for a plurality of depth testing levels, measuring a JNDD of a three-dimensional (3D) display for the plurality of depth testing levels by increasing or decreasing the real size of the object, and generating a JNDD model of the 3D display based on the measurement result.
US09235927B2
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for shading computer graphics (CG) representations of materials. One of the methods includes obtaining data describing a physical material; receiving a shading request to shade a particular point in a CG representation of the physical material from a rendering engine, wherein the request identifies a mapping position of the particular point, a view direction at the mapping position, and a light direction at the mapping position; calculating a direct lighting color at the mapping position using a plurality of palletized images; calculating an indirect lighting color at the mapping position using the data describing the physical material; generating a final color at the mapping position by combining the direct lighting color and the indirect lighting color; and providing the final color to the rendering engine for use in rendering the CG representation of the physical material.
US09235919B2
A system and method of identifying concealed objects using an anthropomorphic display is disclosed. In a particular embodiment, the method includes displaying a software 3-D avatar on a visual display when an individual is detected within a scanning area, where the 3-D avatar is an anthropomorphic representation of the individual. The method also includes scanning the individual with a plurality of concealed object detection sensors viewing the scanning area and identifying at least one area on the individual in response to detecting a concealed object on the individual, where the at least one area in which the concealed object is detected on the individual is visually indicated at a corresponding location on the software 3-D avatar with a computer generated highlight. In addition, the software 3-D avatar is dimmed, modified with text, graphics, colors, textures, opacity, transparency, or any combination thereof, when no individuals are detected in the scanning area.
US09235911B2
Systems and methods for compositing image layers using a GPU shader module. Image layers may be mapped to a destination surface and tiled such that each tile has the same number and kind of mapped image layers. The mapped image layers of a tile may be provided to a shader module, such as a pixel shader, to composite the image layers into display data.
US09235910B2
A graphics rendering and editing apparatus includes a rendering unit configured to render a graphic object, a position specifying unit configured to specify a pre-change position and a post-change position of an arbitrary point on the graphic object, an attribute specifying unit configured to specify a deformation attribute of the graphic object, the deformation attribute being related to how the graphic object is deformed as a position of the arbitrary point changes, and a deformation unit configured to deform, when the position specifying unit has specified the pre-change position and the post-change position the graphic object in accordance with the pre-change position, the post-change position, and the attribute specified by the attribute specifying unit.
US09235909B2
A model simplification tool can receive a command to simplify the presentation of a visually complex semantic model from a graphical modeling application. The visually complex semantic model can be comprised of a multitude of object representations and their associations, such that the usability of the model is impaired. An association status can be determined for each object representation, which can designate the object representation as autonomous, containment, or subordinate. The presentation of the visually complex semantic model can be consolidated based on the association status of object representations. Subordinate objects can be nested within containment objects to produce a simplified semantic model. The simplified semantic model can be rendered within the graphical modeling application.
US09235904B1
An object detector includes a bottom-up object hypotheses generation unit; a top-down object search with supervised descent unit; and an object re-localization unit with a localization model.
US09235899B1
A process generates lookup tables for estimating spatial depth in a scene. The process identifies subsets of illuminators of a camera system that has a 2-dimensional array of image sensors and illuminators in fixed locations relative to the array, and partitions the image sensors into a plurality of pixels. For each pixel, and for each of m distinct depths from the respective pixel, the process simulates a virtual surface at the respective depth. For each of the subsets of illuminators, the process determines an expected light intensity at the pixel based on the respective depth. The process forms an intensity vector using the expected light intensities for each of the distinct subsets and normalizes the intensity vector. For each pixel, the process constructs a lookup table comprising the normalized vectors corresponding to the pixel. The lookup table associates each normalized vector with the depth of the corresponding simulated surface.
US09235896B2
A method for recognizing a target in a sonar image, the method comprising: normalizing a sonar image; using/defining multiple test objects; rotating each test object between multiple positions; using a projection of each test object in each position as a template, so that multiple templates are provided for each test object, each template corresponding to a different rotational position; applying the multiple templates for the multiple test objects to the normalized image; and creating at least one feature vector for the image for use in target recognition.
US09235893B2
The disclosure relates to the field of image processing technologies and particularly to a method and device for determining an image offset and a storage medium. A method according to an embodiment of the disclosure includes: dividing equally an acquired target image into a number M*N of first sub-areas and dividing equally an acquired image to be aligned into a number M*N of second sub-areas; determining an area offset between each first sub-area and a corresponding second sub-area; and determining an image offset between the target image and the image to be aligned according to the determined multiple area offsets.
US09235888B2
A second form of image data is determined from a first form of image data of an examination object in a radiological imaging system. A set of a defined plurality of input pixels in the image data of the first form is determined. In addition, a set of target form parameters of a target form model with a defined plurality of target form parameters is prognostically determined by way of a data-driven regression method from the plurality of input pixels. The number of target form parameters is smaller than the number of input pixels. The second form of image data is determined from the set of target form parameters. There is also described a method in radiological imaging for determining the geometric position of a number of target objects in a second form of image data and an image processing workstation for determining a second form of image data from a first form of image data as well as an imaging device.
US09235875B2
Systems, methods and computer readable media for image enhancement using learned non-photorealistic effects. In some implementations, a method can include obtaining an original image. The method can also include analyzing the original image to determine one or more characteristics of the original image. The method can further include selecting one or more filters based on the one or more characteristics and applying the one or more filters to the original image to generate a modified image. The method can include causing the modified image to be displayed.
US09235869B2
A method and system for tracking goods is provided wherein the system is a transnomic code system. The transnomic code system includes a prescriber interface, a pharmaceutical interface, a pharmacy interface and a management server that communicate via communication mediums, such as an electronic prescribing switch and the Internet. The transnomic code is a dynamic code that includes a tracking code and one or more information sets, wherein each information set includes a read header and extensible content. The transnomic code is assigned to a product, such as a pharmaceutical product. The system allows for adding information sets to the transnomic code at any point during the life-cycle of a product.
US09235857B2
Exemplary embodiment of the present invention would provide systems, including Internet-based systems, and computer-implemented methods, for providing online Buyers and Sellers who physically transact an exchange of an item at a local meeting place, indicia of confirmation of the exchange on which to base a background online payment. In particular, exemplary embodiments of the present invention would provide a way for Buyers and/or Sellers to input an identifier for online authentication to confirm that a physical exchange of an item sold had been transacted and that would accordingly provide an online system with a basis to charge the relevant Buyer's account for a sale amount and pay the Seller for the item sold.
US09235855B2
A computer can receive an alarm event data that results from detection of an event by an alarm system. The alarm event data comprises an identifier for the alarm system. In response to receiving the alarm event data, the computer can access a service subscription account associated with security services for the alarm system. Based on information maintained in the service subscription account, the computer can determine whether a processing service fee is associated with an action of forwarding the alarm event data to a central monitoring station or a mobile computing device associated with the service subscription account. If a processing service fee is associated with the forwarding action, the computer can record the alarm event data and the processing service fee in a record to support a creation of an invoice and forward the alarm event data to the central monitoring station or the mobile computing device.
US09235848B1
Social media networking applications, web sites, and services creates implicit relationships between users based on their interest or participation in real-world and optionally virtual or online activities in addition to explicitly defined peer relationships. User profiles, activity entities, and expressions may be associated with metadata to assist in searching and navigation. Metadata is implicitly associated with user profiles, activity entities, expressions, or other data entities based on user behavior using metadata collector. A metadata collector is a poll, survey, list, questionnaire, census, test, game, or other type of presentation adapted to solicit user interaction. A metadata collector is associated with metadata elements. When users interact with a metadata collector, their user profiles and the data entities included in their interactions become associated with the metadata elements of the metadata collector. These metadata element associations may then be used for any purpose.
US09235847B2
An energy management system identifies one or more energy-load components, and generates an energy-disutility graph for the identified components. The energy-disutility graph can include, for each of a sequence of discrete time instances, one or more vertices that each corresponds to an alternative operating state for a component. Further, an arc that couples two vertices indicates an energy-disutility model corresponding to energy and disutility costs for the component. The energy management system also communicates an energy-demand bid to the energy provider, such that the energy-demand bid includes the energy-disutility graph.
US09235846B2
Disclosed herein are systems and methods for populating a table having null values using a predictive query interface including means for receiving a tabular dataset from a user as input, the tabular dataset having data values organized as columns and rows; identifying a plurality of null values within the tabular dataset, the null values being dispersed across multiple rows and multiple columns of the tabular dataset; generating indices from the tabular dataset of columns and rows, the indices representing probabilistic relationships between the rows and the columns of the tabular dataset; displaying the tabular dataset as output to the user, the displayed output including the data values depicted as known values and the null values depicted as unknown values; receiving input from the user to populate at least a portion of the unknown values within the displayed tabular dataset with predicted values; querying the indices for the predicted values; and displaying the predicted values as updated output to the user. Other related embodiments are further disclosed.
US09235845B2
An apparatus may include a processor and a device state management module. The device state management module may be operative on the processor to receive a trigger signal from a motion sensor in a remote control, to determine the device state of one or more controlled devices and send state management instructions to be transmitted to the one or more controlled devices. The state management instructions may control a set of initial default operations that comprises altering one or more device states in the one or more controlled devices. The apparatus may further include a memory that is arranged to store the determined device state of one or more controlled devices. Other embodiments are described and claimed.
US09235844B2
The present invention provides a method and a system for providing at least one communications service to one or more service providers by a communications service provider. Communications capabilities of the communications service provider are sliced into a plurality of virtual slices and each of the plurality of virtual slices is configured for a different service provider from among the one or more service providers. At least one communications service is provided to each of the one or more service providers through a respective configured virtual slice by the communications service provider. Each of the one or more service providers further provides the communications service to a user through the respective configured virtual slice in collaboration with the communications service provider.
US09235843B2
An intermediary device configured to insert at least one of user interest categories or a client device location in the header portion of a message received from a client device is described herein. The insertion enables a server receiving the message from the intermediary device to target content to the client device based on the at least one of the user interest categories or the client device location.
US09235837B2
A log information management apparatus acquires a card ID from an IC card to set a remaining processing flag to the IC card. The log information management apparatus determines whether the remaining processing flag is set to the IC card before the remaining processing flag is set after the card ID is acquired. The log information management apparatus cause an image forming apparatus to perform a job, and causes a storage device to store a job history based on completion of the performance of the job. The log information management apparatus writes a job history relating to the card ID in the IC card in which the remaining processing flag is determined to be set. The log information management apparatus releases the remaining processing flag after writing the job history.
US09235834B2
Systems and methods are described for performing policy-managed, peer-to-peer service orchestration in a manner that supports the formation of self-organizing service networks that enable rich media experiences. In one embodiment, services are distributed across peer-to-peer communicating nodes, and each node provides message routing and orchestration using a message pump and workflow collator. Distributed policy management of service interfaces helps to provide trust and security, supporting commercial exchange of value. Peer-to-peer messaging and workflow collation allow services to be dynamically created from a heterogeneous set of primitive services. The shared resources are services of many different types, using different service interface bindings beyond those typically supported in a web service deployments built on UDDI, SOAP, and WSDL. In a preferred embodiment, a media services framework is provided that enables nodes to find one another, interact, exchange value, and cooperate across tiers of networks from WANs to PANs.
US09235833B2
Systems and methods are described for performing policy-managed, peer-to-peer service orchestration in a manner that supports the formation of self-organizing service networks that enable rich media experiences. In one embodiment, services are distributed across peer-to-peer communicating nodes, and each node provides message routing and orchestration using a message pump and workflow collator. Distributed policy management of service interfaces helps to provide trust and security, supporting commercial exchange of value. Peer-to-peer messaging and workflow collation allow services to be dynamically created from a heterogeneous set of primitive services. The shared resources are services of many different types, using different service interface bindings beyond those typically supported in a web service deployments built on UDDI, SOAP, and WSDL. In a preferred embodiment, a media services framework is provided that enables nodes to find one another, interact, exchange value, and cooperate across tiers of networks from WANs to PANs.
US09235830B1
In one aspect, a first device includes a processor and a memory accessible to the processor. The memory bears instructions executable by the processor to receive information pertaining to an event to occur at a first date and a first time, establish an entry at an electronic calendar for the event based on the first date and first time, determine a second date and a second time at which to provide a reminder for the event based at least in part on an event type to which the event pertains, and set the reminder to be provided at the second date and second time.
US09235829B2
A method for publishing a message includes receiving, at a first relay, a subscription request from a first client, wherein the subscription request includes a target. The method also includes: recording, at the first relay, subscription information of the first client based on the subscription request; receiving, at the first relay, a publication request from a second client, wherein the publication request includes a message string characterized by a pattern; determining, by the first relay, that the target matches at least a portion of the pattern; determining, by the first relay, if the publication request is a local publication request based on a predetermined policy rule; and transmitting the message string to the first client if the publication request is determined to be a local publication request.
US09235822B2
Various systems, methods, and programs embodied in computer-readable mediums are provided for determining sizes of packaging in a packaging suite employed in a materials handling environment. The packaging may be used, for example, in the shipping of items from the materials handling environment to various destinations. The sizes of the packaging in the packaging suite are determined based at least in part upon the three-dimensional bounding boxes associated with packages or shipments shipped or planned to be shipped from the materials handling environment.
US09235819B2
An information processing apparatus, which is configured to communicate with a server apparatus and an image forming apparatus, comprises a receiving unit configured to receive AR information that includes AR guidance for a first operation of an image forming apparatus, wherein the AR information superimposes the AR guidance on an image that was captured by the information processing apparatus; a display control unit configured to command the information processing apparatus to display the AR guidance to guide a user to operate the image forming apparatus, and an obtaining unit configured to obtain information that originated from performance of the first operation by the image forming apparatus, wherein the receiving unit is further configured to receive AR information that includes additional AR guidance that presents operations for recovering from the error.
US09235814B2
Aspects of the present disclosure relate to management of evaluated rule data sets. Specifically, a unreduced evaluated rule data set may contain a number of items to be compared or analyzed according to a number of rules, and may also contain the results of such analysis. An illustrative reduced evaluated data set can include the results of evaluated rules. When utilized in conjunction with an item data set and a rule data set, the information contained within the unreduced evaluated rule data set may be maintained. The reduce memory requirements of the reduced evaluated rule data set may facilitate storage of the reduced evaluated rule data set in faster to access memory, or may facilitate distributed computation of the reduced evaluated rule data set.
US09235806B2
Techniques for customizing knowledge representation systems including identifying, based on a plurality of concepts in a knowledge representation (KR), a group of one or more concepts relevant to user context information, and providing the identified group of one more concepts to a user. The KR may include a combination of modules. The modules may include a kernel and a customized module customized for the user. The kernel may accessible via a second KR.
US09235800B2
A method for the computer-aided learning of a recurrent neural network for modeling a dynamic system which is characterized at respective times by an observable vector with one or more observables as entries is provided. The neural network includes both a causal network with a flow of information that is directed forwards in time and a retro-causal network with a flow of information which is directed backwards in time. The states of the dynamic system are characterized by first state vectors in the causal network and by second state vectors in the retro-causal network, wherein the state vectors each contain observables for the dynamic system and also hidden states of the dynamic system. Both networks are linked to one another by a combination of the observables from the relevant first and second state vectors and are learned on the basis of training date including known observables vectors.
US09235799B2
Discriminative pretraining technique embodiments are presented that pretrain the hidden layers of a Deep Neural Network (DNN). In general, a one-hidden-layer neural network is trained first using labels discriminatively with error back-propagation (BP). Then, after discarding an output layer in the previous one-hidden-layer neural network, another randomly initialized hidden layer is added on top of the previously trained hidden layer along with a new output layer that represents the targets for classification or recognition. The resulting multiple-hidden-layer DNN is then discriminatively trained using the same strategy, and so on until the desired number of hidden layers is reached. This produces a pretrained DNN. The discriminative pretraining technique embodiments have the advantage of bringing the DNN layer weights close to a good local optimum, while still leaving them in a range with a high gradient so that they can be fine-tuned effectively.
US09235794B2
An information processing device includes a security level determining unit that determines a security level, the security level indicating a level of security related to leakage of information in an image processing device, and an instructing unit that changes an output method to an output method having a high security level and gives at least one of two instructions, in a case where the security level does not satisfy a predetermined condition, the two instructions including an instruction for outputting information notifying the output method that has been changed, and an instruction for outputting information prompting for change of the security level in the image processing device.
US09235793B2
An information processing apparatus which has a first and second mode in which power consumption is lower than that of the first mode is disclosed that includes an accepting unit configured to accept an operation; a display configured to transmit a notification when the apparatus switches from the second mode to the first mode; and a control unit configured to store function data representing function providing units registered; generate, in response to the notification received from the display, a first screen indicating the units and cause the display to display the first screen; store identification data identifying one of the units selected; transmit, in response to the notification received from the display, the notification to the units represented in the function data; and when a response is received from the unit identified in the identification data, cause the display to display a second screen generated by the identified unit.
US09235792B2
High speed reading of fiscal information from memory is enabled while complying with financial regulations. Including fiscal memory 10 that stores fiscal information, a first control unit 5 that controls communication with the host computer 2 and operates at a first processing speed, and a second control unit 7 that controls operation of the fiscal memory 10 and operates at a second processing speed that is lower than the first processing speed, the second control unit 7 performs a write process writing fiscal information received from the host computer 2 to fiscal memory 10, and the first control unit 5 executes a read process reading the fiscal information stored in the fiscal memory 10 without involving processing by the second control unit 7.
US09235787B2
The present invention aims to temporarily change print configuration information easily. To achieve such an object, an information processing apparatus of the present invention comprises: a monitoring unit configured to monitor that job data composed of print configuration information data and content data, and a difference file for temporarily changing the print configuration information of the print configuration information data to different print configuration information are put in a hot folder; and a correcting unit configured to, in a case where the job data and the difference file are put in the hot folder, correct the print configuration information data included in the job data on the basis of the difference file.
US09235783B1
A particular method includes detecting an interaction event using an event capture object of a rendered display of a graphics file. The graphics file is rendered to generate the rendered display by layering one or more foreground objects over one or more background objects. The method also includes executing code associated with the graphics file in response to detecting the interaction event. The code is executed to determine an identifier of a highlight object based on an identifier of the event capture object. The highlight object is below the event capture object in the rendered display and may be below the object to be highlighted in the rendered display. The code is also executed to change an attribute of the highlight object to modify the rendered display.
US09235775B2
Architecture that detects entrances on building facades. In a first stage, scene geometry is exploited and the multi-dimensional problem is reduced down to a one-dimensional (1D) problem. Entrance hypotheses are generated by considering pairs of locations along lines exhibiting strong gradients in the transverse direction. In a second stage, a rich set of discriminative image features for entrances is explored according to constructed designs, specifically focusing on properties such as symmetry and color consistency, for example. Classifiers (e.g., random forest) are utilized to perform automatic feature selection and entrance classification. In another stage, a joint model is formulated in three dimensions (3D) for entrances on a given facade, which enables the exploitation of physical constraints between different entrances on the same facade in a systematic manner to prune false positives, and thereby select an optimum set of entrances on a given facade.
US09235774B2
Methods and apparatus are provided for determining quantization parameter predictors from a plurality of neighboring quantization parameters. An apparatus includes an encoder for encoding image data for at least a portion of a picture using a quantization parameter predictor for a current quantization parameter to be applied to the image data. The quantization parameter predictor is determined using multiple quantization parameters from previously coded neighboring portions. A difference between the current quantization parameter and the quantization parameter predictor is encoded for signaling to a corresponding decoder.
US09235772B2
Notebook comprising a plurality of pages (1) of paper bound together with a cover (2), in which a plurality of substantially vertical and/or substantially horizontal lines are printed on the pages (1) and are formed by a plurality of dots (5) aligned with each other, which have a maximum dimension, in particular diameter, comprised between 0.21 and 0.35 mm, the distance between two adjacent dots (5) of a same line being comprised between 0.43 and 0.7 mm and the color of the dots (5) being darker than the color of the page (1), in which the sum of the four quadrichrome CMYK values of the color of the page (1) is comprised between 0 and 20, in particular comprised between 10 and 20, with the K value less than 10, and the sum of the four CMYK values of the color of the dots (5) is comprised between 15 and 50, in particular between 25 and 40, with the value K less of 40. The present invention also relates to a method for digitizing notes by means of said notebook.
US09235764B2
A candidate output element configured to output recognition target commodities as candidates of a recognized commodity in a descending order of the similarity degrees calculated by the similarity degree calculation element, a distance measurement element configured to measure the distance from the image capturing section to a commodity photographed by the image capturing section, and a changing element configured to change the number of candidates of a recognized commodity output by the candidate output element according to the distance measured by the distance measurement element.
US09235754B2
A person region information extraction unit (101) detects a person region where a person appearing in a video belongs, and generates person region information describing information of the person region. An accompanying person determination unit (102) identifies at least one accompanying person accompanying a tracking target person among persons included in the person region information based on the person region information and information specifying a tracking target person, and generates accompanying person information describing the accompanying person. A distinctive person selection unit (103) selects a distinctive person having a salient feature using the person region information among the accompanying person specified by the accompanying person information, and generates distinctive person information describing the distinctive person. A person tracking unit (104) calculates a tracking result for the distinctive person based on the person region information and the distinctive person information.
US09235751B2
According to one embodiment, a person image processing apparatus includes: an input processor configured to input a plurality of pieces of image data captured at different times by an image capture module; an extraction module configured to extract a person display area showing a same person from each of the pieces of image data captured at the different times; a feature detector configured to detect a feature point showing a feature of a part of a person from the person display area extracted from each of the pieces of image data and acquire reliability of the part shown in the feature point; and a correction module configured to, when correcting the person display area subjected to input processing by the input processor, perform weighting based on the reliability of the feature point included in the person display area.
US09235747B2
An integrated leadframe and bezel structure includes a planar carrier frame, a plurality of bonding leads, a die pad region, and a bezel structure. The bezel structure includes a bending portion shaped and disposed to facilitate a portion of said bezel structure being bent out of the plane of said carrier frame. A sensor IC may be secured to the die pad region, and wire bonds made to permit external connection to the sensor IC. The bezel structure includes portions which are bent such that their upper extent is in or above a sensing surface. The assembly is encapsulated, exposing on the top surface part of the bezel portions and the upper surface of the sensor IC, and on the bottom surface the contact pads. Two or more bezel portions may be provided, one or more on each side of the sensor IC.
US09235746B2
A method for performing user authentication by using a fingerprint in an electronic device is provided. The method includes obtaining fingerprint image and fingerprint position information corresponding to an area of the user's finger, comparing the fingerprint image obtained by using fingerprint position information with a pre-registered fingerprint image corresponding to the position of the area to thereby perform the user authentication, and pairing the fingerprint image corresponding to the area of the user's finger with the fingerprint position information to be thereby stored in the memory.
US09235743B2
An image generating method performed by a computer, includes extracting data corresponding to a first coded image from first image data including the first coded image; generating a second coded image corresponding to the extracted data, wherein a size of a configuration element included in the second coded image is an integral multiple of a dot size of the first image data; and generating second image data indicating an image including an image indicated by the first image data and the generated second coded image.
US09235713B2
The present invention relates to the field of computers, and disclosed are a method, device, and system for encrypting and decrypting an image. The method for encrypting an image includes: encrypting a preset size of header data of a to-be-encrypted image, and obtaining an encrypted data corresponding to the header data; determining a storage location for saving the encrypted data, saving the encrypted data in the storage location, and acquiring an offset for saving the encrypted data; and placing the encryption identifier and the offset in a storage area of the preset size of the to-be-encrypted image, so as to encrypt the to-be-encrypted image. The system includes: a device for encrypting an image and a device for decrypting an image. The present invention is capable of improving the speed and efficiency of encrypting and decrypting an image.
US09235710B2
A method is provided in one example embodiment and includes storing secure boot variables in a baseboard management controller; and sending the secure boot variables to a basic input/output system (BIOS) during a power on self-test, where the BIOS utilizes the secure boot variables during runtime to authenticate drivers and an operating system loader execution. In particular embodiments, the secure boot variables may be included in a white list, a black list, or a key list and, further, stored in erasable programmable read only memory.
US09235709B2
A method and apparatus for protecting the integrity of a mobile terminal are provided. The mobile terminal includes a secure world for preventing unauthorized access to resources, and a normal world other than the secure world. The integrity protection method for the mobile terminal includes sensing a power-on of the mobile terminal, verifying, by a trusted entity in the normal world, the integrity of a first subsequent entity, and sending, when an integrity breach is detected in the first subsequent entity, by the trusted entity, a modification indication signal to the secure world.
US09235708B2
A client hosted virtualization system includes a full volume encryption (FVE) storage device, a processor, and non-volatile memory with BIOS code and virtualization manager code. The virtualization manager initializes the client hosted virtualization system, authenticates a virtual machine image, launches the virtual machine based on the image, receives a transaction from the virtual machine targeted to the FVE storage device, sends the transaction to the FVE storage device, receives a response from the FVE storage device, and sends the first response to the first virtual machine. The client hosted virtualization system is configurable to execute the BIOS or the virtualization manager.
US09235699B2
A computer system includes a first communication unit which communicates with an authentication module storing preset first authentication information, a second communication unit which is connected with a server through a network, the server storing preset second authentication information, a main board unit which implements a preset first operation of a computer, and a controller which receives the first authentication information from the authentication module through the first communication unit, receives the second authentication information corresponding to the first authentication information from the server through the second communication unit, and controls the main board unit to block implementation of the first operation when at least one of the first authentication information and the second authentication information is not received.
US09235690B2
Devices, systems, and methods are provided for remote visualization of the storage compartments in a medication dispenser device, to monitor a patient's compliance with a medication dosage schedule and for verifying the proper loading of medication into the patient's medication dispenser device. The device may include a plurality of storage compartments, each having an interior space for storing at least one medication or medication reminder marker; an image capturing device (e.g., a camera) positionable to capture an image of the interior space of each storage compartment; and a communications module for electronically transmitting the captured image to a central monitoring station.
US09235678B2
A method and an apparatus from such method for designing an integrated circuit (IC) that mitigates the effects of process, voltage, and temperature dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits. Conventional design process takes into account power supply voltage Vdd as a variable that must be considered in a skewed corner analysis. The disclosure teaches that the IC design process can be substantially simplified by essentially factoring out voltage based variations in corner lot analysis for IC designs that include dynamic voltage scaling circuitry, because each fabricated IC die of an IC design having dynamic voltage scaling can individually adjust the applied supply voltage Vdd within a range to offset local process-induced variations in the performance of that specific IC die.
US09235673B2
An apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium are provided. The apparatus comprises an input for receiving an hierarchical integrated circuit design, a selector for selecting a candidate output pin, a cloner for adapting the hierarchical integrated circuit design, a re-connector for adapting the hierarchical integrated circuit design, and an output for outputting the adapted hierarchical circuit design. Optionally, the apparatus comprises a timing improver. The apparatus selects a candidate output pin of an IP block that is a node on at least two timing paths that have contradictory timing violations. The candidate output pin is cloned and at least one of the timings paths is connected to the cloned output pin for one of the instances of the IP block.
US09235672B2
An analysis unit analyzes a source code representing design data of a semiconductor device, and generates information (CDFG information) indicating the data and control flow of the semiconductor device. A high-level synthesis data generation unit acquires intermediate data (an object file), which is obtained by compiling the source code, generates intermediate data (an object file) by incorporating the CDFG information generated by the analysis unit into the acquired intermediate data, and outputs the generated intermediate data as high-level synthesis data.
US09235668B1
A computer implemented method for calculating a charge density q1 of a first gate of a double gate transistor comprising a thin body with a first and a second gate interface, the method including determining, using a physical processor, an initial estimate q1,init of the charge density of the first gate; performing, using the physical processor, at least two basic corrections of the initial estimate based on a Taylor development of a function fzero(q1) able to be nullified by a correct value of the charge density q1 of the first gate.
US09235667B2
A model for simulating the electrical behavior of a thyristor includes a model of an NPN bipolar transistor whose emitter forms the cathode of the thyristor and the base forms a low-side control terminal of the thyristor, and a model of a PNP bipolar transistor whose emitter forms the anode of the thyristor and the base forms a high-side control terminal of the thyristor, the collector of the PNP transistor being connected to the low-side control terminal and the collector of the NPN transistor being connected to the high-side control terminal. The transistor models are present a small signal behavior over the entire range of anode currents of the thyristor, whereby the transistor models exhibit a gain drop when the anode current exits the small signal range.
US09235663B2
A method for estimating the quantity of light received by a point M of a heterogeneous participating media, the light being emitted by a light environment. Thereafter, the method comprises estimating, for each point of a first set of points, first values representative of the light attenuation between the considered point and a first surface bounding the media along a plurality of particular directions of light emission, estimating first coefficients of projection by projection of the first values of reduction of light intensity in an orthonormal basis of spherical functions, estimating second values representative of the light attenuation between the point and a second surface along directions, the second surface comprising some of the points of the neighborhood of the point, and estimating the quantity of light received by the point using first coefficients of projection and second values of reduction of light intensity.
US09235658B2
Automated fixture layout is approached in two distinct stages. First, the spatial locations of clamping points on the work piece are determined to ensure immobility of the fixtured part under any infinitesimal perturbation. Second, spatial locations are matched against a user-specified library of reconfigurable clamps to synthesize a valid fixture layout or configuration that includes clamps that are accessible and collision free. The spatial locations matching during the second stage can be the same spatial locations chosen in the first stage to ensure immobility, or a different set of spatial locations.
US09235656B2
It is provided a computer-implemented method for designing a CAD modeled object. The method comprises displaying at least one three-dimensional parametric shape; user-interacting with the screen; defining on a support at least one stroke corresponding to the user-interacting; selecting a number of the three-dimensional parametric shapes; evaluating a relative position of the stroke with the selected shape; and determining a geometrical CAD operation based on the number and the relative position. Such a method makes the design of a CAD modeled object easier.
US09235653B2
Systems and methods identify recent or ephemeral events involving entities that can be used to update a data graph or provide enhanced search results. For example, a computer-implemented method includes determining at least one search term for an entity in a data graph and determining a time period having an increase in queries for the at least one search term, the increase meeting a threshold. The method may include determining documents having dates associated with the time period, the documents being responsive to the at least one search term, and analyzing the documents to determine a subject, verb, object triple, where the search term corresponds to the subject or the object of the triple. The method may also include providing an update for the data graph based on the triple. The method may also include generating text describing the triple for inclusion in a search result for the search query.
US09235650B2
Methods for product data management and corresponding systems and computer-readable mediums. A method includes receiving an XML document by a parallel parser process, the XML document including a plurality of elements of an XML data structure that corresponds to an object model. The method includes dividing the XML document into a plurality of chunks using the parallel parser process, and parsing the plurality of chunks in parallel using separate parsing tasks to produce objects representing the elements and corresponding attributes. The method includes storing the objects and corresponding attributes in a persistent element store.
US09235647B1
A computer-implemented method for predictive responses to internet object queries may include receiving a query from a client to evaluate a first internet object. The computer-implemented method may also include analyzing the query to predict a set of additional internet objects for which the client may subsequently request an evaluation. The computer-implemented method may further include transmitting an evaluation of the first internet object and of each additional internet object in the set of additional internet objects to the client. Various other methods, systems, and computer-readable media are also disclosed.
US09235645B1
The illustrative embodiments described herein provide systems and methods for managing the execution of processing jobs. In one embodiment, a method includes receiving a processing job associated with a set of processing job parameters. The processing job is sent from a user interfacing device associated with a user. The method also includes determining a processing job priority for the processing job using the set of processing job parameters, identifying a destination processing device capable of executing the processing job using the set of processing job parameters, and initiating execution of the processing job at the destination processing device to form processed data in response to determining to execute the processing job based on the processing job priority.
US09235636B2
Disclosed are systems, methods, and non-transitory computer-readable storage media for executing a database query based on an incomplete query. An example system configured to practice the method receives a web request, wherein a uniform resource locator (URL) of the web request provides an argument, and extracts the argument from the URL as a parameter for a database query. The system identifies an unspecified parameter in the database query, and selects a likely value for the unspecified parameter. Then the system executes the database query using the parameter and the likely value, and incorporates at least part of the query result in a web page served in response to the web request. The system can cache the web request and the likely value for the unspecified parameter for later use.
US09235633B2
Data of a database environment, which includes hierarchy information and a matrix of values, is processed. The hierarchy information includes at least two sets of identification codes and defines at least two groups of identification codes. The matrix of values includes at least two columns of identification values. At least one simple filter object is generated based on a user input. Each simple filter object defines an ad hoc group of identification codes selected from a respective one of the sets of identification codes. A filtered operation object that specifies an operation and at least one of the simple filter objects is generated based on a user input. Each of the ad hoc groups differs from each of the groups defined by the hierarchy information.
US09235632B1
A computer implemented method, computer program product, and system for data replication comprising directing Input/Outputs (I/Os) intercepted by a splitter to a synchronizer, directing initialization data to the synchronizer from an initialization process, determining, at the synchronizer, whether the data arrived from the initialization process has been overwritten by the splitter, based on a determination that the data has been overwritten, discarding the data and based on a determination that the data has not been overwritten, sending the data to a Logical Unit.
US09235630B1
An initial work package is obtained. The initial work package defines at least one hypothesis associated with a given data problem, and is generated in accordance with one or more phases of an automated data analytics lifecycle. A plurality of datasets is identified. One or more datasets in the plurality of datasets that are relevant to the at least one hypothesis are discovered. The at least one hypothesis is tested using at least a portion of the one or more discovered datasets.
US09235623B2
Policy-based storage and retrieval combined with a distribution algorithm results in automatic and even distribution of policy-based storage structures across a set of nodes and dynamic, automated homing or ownership of policy-based storage structures. Large numbers of policy-based storage structures may be distributed without manual administration, allowing for rapid creation and destruction of storage structures. The overall load may be distributed and balanced across the server pool. Multiple entries having the same key value in a database- or table-like structure allow for distribution of policy-based storage and retrieval by key value and for queue semantics to be utilized for microqueues in the large database- or table-like structure.
US09235609B1
A local data store may also be configured to process updates using a common API with reference to a common schema. The common API and common schema may also be employed by hosted applications utilizing a remote distributed data store. Behavior of the remote distributed data store may be emulated by the local data store. Behaviors of the distributed data store that may be simulated include eventual consistency, provisioned throughput and latency based on horizontal partitioning.
US09235600B2
A digital image of the object is captured and the object is recognized from plurality of objects in a database. An information address corresponding to the object is then used to access information and initiate communication pertinent to the object.
US09235594B2
Embodiments of the invention relate to synchronization of data in a shared pool of configurable computer resources. An image of the filesystem changes, including data and metadata, is captured in the form of a consistency point. Sequential consistency points are created, with changes to data and metadata in the filesystem between sequential consistency captured and placed in a queue for communication to a target filesystem at a target site. The changes are communicated as a filesystem operation, with the communication limited to the changes captured and reflected in the consistency point.
US09235591B2
Various exemplary embodiments relate to a method of compressing location data. The method may include: receiving original location data; selecting a contextual profile based at least in part on the original location data; selecting a compression method based on the contextual profile; and converting the original location data to a compressed format based on the compression method. Various exemplary embodiments relate to a system for compressing location data. The system may include: a location receiver configured to generate original location data based at least on signals from global navigation satellite system (GNSS) satellites; a location engine configured to select a contextual profile based at least in part on the original location data; and a contextual compression filter configured to generate compressed location data in a compressed format based on the selected contextual profile.
US09235590B1
A database system may implement compression management of tables in the database system. The compression management may include determination of a pattern of usage of various database tables in the database system. Based on this pattern of usage, the database tables may be selected as candidates for compression or decompression at the appropriate time. In one example, the pattern of usage may be based on the contents of a query log of the database system. The compression management may also include evaluation of various compression strategies to apply to a candidate database table. Each compression strategy may be evaluated to determine if application to a database table or a portion of the database table would be beneficial based on various conditions. The compression management may also include consideration of each available compression strategy to be applied solely or in combination with one another.
US09235589B2
Mechanisms for optimizing the storage allocation in a virtual desktop environment (VDE) managing a shared storage capacity, are provided. The shared storage capacity includes previously stored files, each being associated with a respective unique first file identifier, the VDE providing a virtual desktop to a processing device of a user. Upon reception of a first write request for writing a second file specified in the request, a second file identifier of the specified second file is determined and compared with the first file identifier of any first file stored to the shared storage capacity. A pointer to the stored first file associated with that first file identifier is created if the second file identifier is identical to one of the first file identifiers and, if not, the specified second file associated with the second file identifier is stored in the shared storage capacity.
US09235581B2
A cluster system includes a plurality of computing nodes connected to a network. Each node is configured to access its own storage device, and to send and receive input/output (I/O) operations associated with its own storage device. Further, each node of the plurality of nodes may be configured to have a function of acting as a first node, which sends a first message to other nodes of the plurality of nodes. The first message may include configuration information indicative of a data placement of data on the plurality of nodes in the cluster system according to an event. Following receipt of the first message from the first node, each of the other nodes may be configured to determine, based at least in part on the configuration information, whether data stored on its own storage device is affected by the event.
US09235579B1
Various embodiments of a system and method for archiving data items to one or more archival storage devices are described. According to some embodiments of the method, an archival software application may implement a plurality of producer agents, where each of the producer agents is executable to produce items of a different type. The archival software application may also implement a plurality of archiving agents for archiving the items produced by the producer agents to one or more archival storage devices. In some embodiments each of the archiving agents may be executable to archive any item of any type produced by the producer agents. The archival software application may also implement a plurality of indexing agents executable to create a searchable index of the items archived to the one or more storage devices.
US09235571B2
According to various embodiments, a mobile device continuously and/or automatically scans a user environment for tags containing non-human-readable data. The mobile device may continuously and/or automatically scan the environment for tags without being specifically directed at a particular tag. The mobile device may be adapted to scan for audio tags, radio frequency tags, and/or image tags. The mobile device may be configured to scan for and identify tags within the user environment that satisfy a user preference. The mobile device may perform an action in response to identifying a tag that satisfies a user preference. The mobile device may be configured to scan for a wide variety of tags, including tags in the form of quick response codes, steganographic content, audio watermarks, audio outside of a human audible range, radio frequency identification tags, long wavelength identification tags, near field communication tags, and/or a Memory Spot device.
US09235569B1
A computer-implemented technique can include executing a web-based application and receiving a request to translate at least a portion of the web-based application. In response to receiving the request, the technique can include identifying text portions in the web-based application, transmitting the text portions to a server, wherein receipt of the text portions causes the server to match the text portions to entries in a database associated with the server to obtain UI strings, and receiving the UI strings from the server. In in response to receiving the UI strings, the technique can include providing an indicator of a particular UI string when the particular UI string is displayed during execution of the web-based application. The technique can also include receiving a selection of the particular UI string, and outputting metadata associated with the particular UI string, the metadata representing context information for assisting a human translator.
US09235565B2
Techniques for constructing a set of customized dictionaries for a particular user are described. Each of the customized dictionaries in the set may include a different blending of one or more frequently used words collected from texts submitted by one or more users. A copy of the set of customized dictionaries may be sent to each of a plurality of electronic devices associated with the particular user to be stored on the electronic device and to aid the particular user in inputting text to the electronic device.
US09235552B1
Techniques are disclosed for producing a collaborative recording of an audio event. An online server or service identifies participating mobile devices with recording capabilities that are available for recording at least a portion of the audio event. The online server or service determines the locations of the potential participating mobile devices, and identifies ranges of frequencies to be recorded by each of the participating mobile devices. The individual recordings are then compiled into a final collaborative recording.
US09235551B2
Machine-implemented methods, systems, processing devices and machine-readable media are provided for simulating a mill reline, which involve collecting mill relining data and processing the relining data as simulation parameters using a mill relining model. The relining data generally include variables treated as discrete time/frequency distributions. Simulated events for the mill reline may be generated based on the relining data. Additional relining data relating to a specific existing site may be included as simulation parameters. The simulation may be used in determining an optimal work flow for carrying out the mill reline at a specific existing site, e.g., where time to carry out the mill reline is minimized. The simulation may also be employed for benchmarking. The additional relining data may be provided in video format, and analysis of the video format data may be undertaken, e.g., by an operator for refining and/or verifying the additional relining data, prior to utilizing the additional relining data as simulation parameters in the simulation model. The mill relining data may also include additional parameters, such as the size and quantity of the liners, the reline planning process and relining crew proficiency, the relining equipment and plant design surrounding the mill being relined, and the like.
US09235550B2
A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
US09235545B2
A communication system where first and second devices communicate concurrently and bidirectionally over a single wire and a ground. The second device can be a computing device having a powered component which requires a certain power output, for instance, and the first device may be a power supply unit. The second device provides a signal on a control line (the single wire) which is characterized by a frequency, pulse width, duty cycle and/or an amplitude which is associated with a message from the second device. The first device recognizes the message in the signal and invokes a corresponding function, such as by enabling a corresponding power supply. The power supply provides power to the second device via a separate power line. Further, the first device modifies the signal, without adding power, to provide a message from the first device, concurrent with the message from the second device.
US09235542B2
A signal switching circuit allows a PCIe card access to additional data channels when installation of the PCIe cards on first and second PCIe connectors are detected. First and second PCIe connectors output a first detection signal when each of the first and second PCIe connectors receives a PCIe card. The first and second PCIe connectors output a second detection signal when each of the first and second PCIe connectors does not receive a PCIe card. A first multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the first multiplexer, to transmit PCIe signals to the first or second PCIe connector. A second multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the second multiplexer, to transmit PCIe signals to the first or second PCIe connectors.
US09235539B2
A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.
US09235536B2
While making it possible to register generation information used to generate a Web page for each topic by sending element information being components of the Web page by an email and add element information to the generation information by an email, it is made difficult for persons other than a person who registered the generation information to add the element information. When a receiver address included in a received email is a first address, an information registration apparatus registers generation information included in the email and transmits an email including a unique second address corresponding to the generation information to a sender of the received email, and when the receiver address is a second address and the receiver address is not the same as receiver addresses included in emails received before, the information registration apparatus adds element information to the generation information corresponding to the receiver address included in the currently received email.
US09235535B1
Techniques for reducing overheads of primary storage transferring during a backup by transferring in an out-of-order manner are described herein. According to one embodiment, in response to a request at a primary storage for a backup of a plurality of data blocks, a transfer order of dirty data blocks is determined based on an access assessment of the dirty data blocks, wherein the dirty data blocks are data blocks of the plurality of data blocks that have been changed from a previous backup, and wherein the transfer order is different from a sequential logical order of the dirty data blocks provided by the primary storage. Then the dirty data blocks are transferred to a secondary storage in the determined order.
US09235521B2
A cache controller configured to detect a wait type (i.e., a wait event) associated with an imprecise collision and/or contention event is disclosed. The cache controller is configured to operatively connect to a cache memory device, which is configured to store a plurality of cache lines. The cache controller is configured to detect a wait type due to an imprecise collision and/or collision event associated with a cache line. The cache controller is configured to cause transmission of a broadcast to one or more transaction sources (e.g., broadcast to the transaction sources internal to the cache controller) requesting the cache line indicating the transaction source can employ the cache line.
US09235509B1
The various implementations described herein include systems, methods and/or devices used to enable write amplification reduction by delaying read access to data written during garbage collection. In one aspect, read access to a write unit to which data was written during garbage collection is delayed until a predefined subsequent operation has been completed.
US09235508B2
Techniques are generally described related to a flash-based buffer management strategy. One example method to manage a buffer for a computer system may include maintaining a page-action list for monitoring a plurality of operations being executed on the computer system and utilizing a plurality of buffer pages of the buffer. An example page-action list may contain a hot-access queue for recently accessed buffer pages and a cold-access queue for less accessed buffer pages. The example method may also include, upon a determination that the buffer is full, identifying a victim buffer page from the plurality of buffer pages for eviction and evicting the victim buffer page from the buffer. The victim buffer page may be selected from the cold-access queue and based on a page weight, which is calculated based on a page state of the specific buffer page and a page hotness prediction for the specific buffer page might be accessed by an incoming operation.
US09235487B2
A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.
US09235486B1
Techniques for spare storage pool management are disclosed. In one particular embodiment, the techniques may be realized as a method for spare storage pool management comprising receiving spare storage configuration information for a storage drive pool comprising a plurality of storage drives, maintaining spare storage mapping information to spare storage within the storage drive pool based at least in part on the spare storage configuration information, monitoring spare storage within the storage drive pool for detecting block failures within the storage drive pool, detecting a failure of a block in a first storage drive of the plurality of storage drives, and updating the spare storage mapping information associated with the failed block in the first storage drive to map to a spare block in a second storage drive of the plurality of storage drives.
US09235483B2
A secondary storage controller receives metadata that uniquely identifies a source volume of a primary storage controller. Data stored in the source volume of the primary storage controller is synchronously copied to a target volume of the secondary storage controller. The secondary storage controller receives a command from a primary host to write selected data to the source volume. In response to receiving the command at the secondary storage controller, the selected data is written to the target volume of the secondary storage controller.
US09235480B1
Techniques for providing incremental backup restoration are disclosed. In one particular exemplary embodiment, the techniques may be realized as a computer implemented method for providing incremental backup restoration comprising setting one or more allocated electronic storage indicators each indicating an allocated portion of electronic storage, comparing the one or more allocated electronic storage indicators with one or more prior backups in reverse chronological order starting from a most recent backup and proceeding until all of the one or more allocated electronic storage indicators have been identified in the one or more prior backups, and restoring the one or more prior backups corresponding to the one or more allocated electronic storage indicators.
US09235475B1
In one embodiment, in response to a list of a plurality of fingerprints representing data chunks to be replicated from a source storage system to a target storage system over a network, one of the fingerprints is selected as a representative fingerprint that matches selection criteria. The source storage system generates a fingerprint representation for each of the fingerprints that is smaller than the corresponding fingerprint. The representative fingerprint and the fingerprint representations are transmitted to the target storage system over the network, without transmitting all full fingerprints of the data chunks, to allow the target storage system identifying which of the data chunks are missing. In response to information received from the target storage system indicating one or more data chunks that are missing at the target storage system, the missing data chunks are then transmitted to the target storage system.
US09235474B1
Some of the methods provided herein may include periodically revising a mirror of the target computing system, according to a predetermined backup schedule, the mirror being stored on the virtual failover volume resident on an appliance that is operatively associated with the target computing system, by periodically comparing the mirror to a configuration of the target computing system to determine changed data blocks relative to the mirror, storing the changed data blocks as one or more differential files in the virtual failover volume, and incorporating the changed data blocks into the mirror. In some embodiments, the systems and methods may be utilized to resparsify the virtual failover volume.
US09235471B2
Technology is disclosed for performing background initialization on protection information enabled storage volumes or drives. In some embodiments, a storage controller generates multiple I/O requests for stripe segments of each drive (e.g., disk) of multiple drives of a RAID-based system (e.g., RAID-based disk array). The I/O requests are then sorted for each of the drives according to a pre-determined arrangement and initiated in parallel to the disks while enforcing the pre-determined arrangement. Sorting and issuing the I/O requests in the manner described herein can, for example, reduce drive head movement resulting in faster storage subsystem initialization.
US09235465B2
Systems and methods are disclosed that facilitate storage and retrieval of data to/from memory with permanent faults. Permanent “stuck at” faults, associated with individual bits, interfere with Write operations. A memory bit with the SA-0 fault does not store the value “1” while a memory bit with the SA-1 fault does not store the value “0”. Hence, when later retrieved by a Read operation, stored data located on one or more bits having a permanent fault may be different from the data that was originally written. Techniques are disclosed that facilitate correct retrieval of data in the presence of “stuck at” faults by keeping track of the positions of the bits that are stuck at a value different from the ones that are written and then, at Read time, inverting the values read from those positions.
US09235464B2
A database server includes logic that is operable to monitor and analyze at least events occurring within an environment of the database server and/or execution errors generated by the database server in order to detect whether a problem condition exists. The database server further includes logic that is operable to send one or more commands to a database driver of a client that is communicatively connected to the database server, the one or more commands specifying one or more actions to be taken by the database driver in response to the existence of the problem condition. The database driver includes logic that is operable to receive the one or more commands from the database server and logic that is operable to cause the one or more commands to be executed.
US09235461B2
Hardening of an integrated circuit such as a GPU processor to soft errors caused by particle strikes is applied selectively to the set of devices according to the magnitude of error resulting from this soft error for the particular device. This approach differs from approaches that protect all devices, all devices likely to produce an output error, or all devices that are vulnerable.
US09235457B2
A method and apparatus for proactively communicating information between processes through a message repository is provided. To communicate with other processes, a process may post a message to a message repository. Other processes may, at regular or irregular intervals, search the message repository for new messages that have been posted to the repository since the last search, and retrieve those new messages. Processes may post and retrieve messages relative to the message repository by invoking methods provided by an application programming interface (API). By posting a message to the message repository, a particular process can inform other interested processes proactively of actions that the particular process has taken, is taking, or will take. By retrieving messages from the message repository, a process can determine what actions other processes have taken, are taking, or will take, and adjust accordingly.
US09235456B2
A technique is specified for configuring an electronic control unit having intercommunicating applications which have been arranged in various partitions and to which differing safety integrity levels have been assigned. According to one method aspect, the communications behavior of the applications assigned to the differing partitions amongst themselves is analyzed, in order to identify data-writing and data-reading applications that are not located in the same partition. Subsequently, a shared memory area for the intercommunicating applications is configured, and a to communications data structure for the applications is generated. The communications data structure is at least partially arranged in the shared memory area.
US09235455B2
Embodiments of an apparatus including a first processor core having a local agent running thereon, the agent comprising a local process and a proxy agent and a second processor core having a remote agent running thereon, the remote agent being an instance of the local agent. A shared memory wherein coupled to the first processor core and the second processor core, wherein the local agent and the remote agent communicate via the shared memory. Other embodiments are disclosed and claimed.
US09235453B2
A disclosed information processing system includes a first apparatus including a storage unit storing types of events which occur in the first apparatus so as to be reported to an information processing apparatus via a network, and a sending unit sending, when one of the events stored in the storage unit occurs, event information of the event to the information processing apparatus; and the information processing apparatus including a delivery destination storage unit storing identification information of a second apparatus existing at a delivery destination of the event in the first apparatus, and a delivery unit sending the event information of the event to the second apparatus of which identification information is stored in the delivery destination storage unit when the event information is received by the information processing apparatus.
US09235452B2
Methods and systems are disclosed in which bitmap data transmission is improved by using some of the advantages of primitive remoting, thus allowing for the reduction of the bandwidth and processing needed to remote a virtual desktop experience. In an embodiment, rendering is performed and bitmaps are remoted, but metadata comprising shortcuts or hints are provided to assist in the rendering of the bitmap data.
US09235444B2
Global heap allocation technologies in a multi-thread environment, and particularly a method for dynamically adjusting global heap allocation in the multi-thread environment, and more particularly to a method and system for dynamically adjusting global heap allocation by monitoring conflict parameters of the global heap allocation method. Specifically, a method of dynamically adjusting global heap allocation in multi-thread environment, comprising: identifying a global heap allocation method in an application program; judging whether the global heap allocation method is a multi-thread conflict hot point; and using a local stack to allocate memory space requested by the global heap allocation method in response to a “yes” judging result. The method is adapted to purposefully dynamically adjust the intrinsic global heap allocation method in the program according to a real-time running state, reduce the lock contention on the global heap, and effectively improve a resource allocating efficiency and a resource utilization rate.
US09235433B2
A method for optimizing code includes receiving, by a compiler and from an interpreter, a code section representation including an object allocation, compiling, by the compiler, the code section representation into machine code with a compact allocated object of the object allocation, and triggering a deoptimization returning execution to the interpreter in response to an attempted access of the compact allocated object. The method further includes setting, by the interpreter and within the code section representation, a flag indicating that a new compact allocated object is required at a location of the attempted access, receiving, by the compiler, the code section representation including the flag, compiling, by the compiler and according to the flag, the code section representation into new machine code including the new compact allocated object, and executing the new machine code with the new compact allocated object.
US09235425B2
A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.
US09235424B1
A method includes performing operations as follows on a processor: defining a bearing map having an axis corresponding to a first metric, the first metric being based on system management performance for a first defined time interval, defining an object sketch map corresponding to a second metric, the second metric being based on system management performance for a second defined time interval, and combining the bearing map and the object sketch map so as to generate a cognitive map. The cognitive map includes a data object having a position on the axis based on a first value for the first metric and an appearance based on a second value for the second metric.
US09235420B2
Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed.
US09235419B2
Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry.
US09235417B2
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing Real Time Instruction Tracing compression of RET instructions For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets describing the instruction tracing; and means for compressing a multi-bit RET instruction (RETurn instruction) to a single bit RET instruction.
US09235408B2
Updating software on first and second network controller entities (NCEs), without disrupting traffic processing, comprises resetting the second NCE after it receives a proposed software version from the first NCE. The second NCE runs the proposed software version in a standby role. While the second NCE runs the proposed software version in the standby role, databases of the NCEs stay synchronized. Resetting the first NCE induces the second NCE to assume the master role, and the first NCE to assume the standby role. The second NCE in the master role tests the proposed software version for a predetermined period. If validation succeeds, the second NCE instructs the first NCE to reboot and run the proposed software version in the standby role. Otherwise, the second NCE reverts to running the current software version in the standby role; and the first NCE, running the current software version, reverts to the master role.
US09235406B2
Methods and apparatus for accepting software updates without interruption of ongoing services. Various embodiments are adapted for maintaining service continuity in multi-mode devices such as cellular devices. In one exemplary implementation, unlike prior art solutions (which interrupt user identity module software to implement changes to the network access software), unnecessary updates can be postponed or otherwise scheduled so as to minimize or eliminate service or user experience impact.
US09235403B2
A mechanism that allows firmware for a computing device to be updated in a secure manner by utilizing an update validation procedure included in a ROM image is discussed.
US09235397B2
Provided are a method and apparatus for increasing task-execution speed, and, more particularly, a method and apparatus for increasing task-execution speed by compiling code to bytecodes, and executing native code in units of blocks instead of bytecodes, in which a block is a group of a series of bytecodes. The apparatus includes a receiving unit which receives a bytecode, a control unit which identifies whether the received bytecode is the last bytecode of a block, and a transmitting unit which transmits an address of a first native code of one or more native codes that correspond to one or more bytecodes included in the block based on the identification result.
US09235396B2
A data partitioning plan is automatically generated that—given a data-parallel program and a large input dataset, and without having to first run the program on the input dataset—substantially optimizes performance of the distributed execution system that explicitly measures and infers various properties of both data and computation to perform cost estimation and optimization. Estimation may comprise inferring the cost of a candidate data partitioning plan, and optimization may comprise generating an optimal partitioning plan based on the estimated costs of computation and input/output.
US09235386B2
In general, techniques are described that facilitate the reuse of software assets within an enterprise. A software asset, as used herein, refers to a set of one or more related artifacts that have been created or harvested for the purpose of applying that asset repeatedly in subsequent development environments. A system, for example, is described that includes a repository to store artifacts, and an asset source to generate a software asset based on the artifacts. The system further includes an asset management system to receive the software asset from the asset source and store the software asset within an asset library. The system may further include a model having one or more elements, and an asset retrieval module to selectively retrieve a subset of the software assets from the asset library based on input from a user identifying one or more of the elements.
US09235382B2
Input filters correlate to target components. For a given target component, the input filter defines input validation information. The input filter might also define conversions or transformations to be applied to valid input prior to being provided to the target component. At build time, code is accessed that contains the input validation, conversion and transformation and that identifies the associated target component. The information is then used to construct an input filter. At run time, when an input processing component receives an input, the input processing component identifies the target component, accesses the associated input filter, and uses the information contained in the input filter to determine whether the input is valid, and whether and how to convert and transform the value.
US09235379B2
A system and associated method for generating a Service Component Architecture (SCA) module with Service Oriented Architecture (SOA) model elements. A service model is created according to a process model that has activities and a process flow. Services of the service model are respectively associated with the activities. Each service is determined to employ only one service operation definition to render a message specification of a respective activity that is associated with each service. The activities, the process flow, and the message specification are utilized to produce the SCA module in executable implementations.
US09235364B2
An apparatus and method of forming an image for image-forming data includes connecting the image-forming apparatus to a device by using a wireless communication, receiving image-forming data from the connected device; adjusting a priority order of the image-forming data that is received from the device, according to a type of the device or a mode in which the image-forming apparatus is connected to the device, and based on the adjusted priority of the image-forming data, forming an image for the image-forming data.
US09235361B2
A printer includes a printing unit, a paper feeding unit, a display unit and a control unit. The printing unit is configured and arranged to execute printing. The paper feeding unit is configured and arranged to hold paper. The display unit is configured and arranged to display a paper registration screen for registering or confirming attributes of the paper according to an operation on the paper feeding unit. The control unit is configured not to display the paper registration screen when non-display conditions have been satisfied even when the operation is performed.
US09235354B2
A storage network system that prevents waste of a core's resources and is thereby operated efficiently, and a method for controlling such a storage network system are provided.Policy differences between a core and a plurality of edges are buffered by enabling hierarchical control of data storage on the side of the plurality of edges in cooperation with hierarchical control of data storage on the core side, and the buffered policy is applied to the hierarchical control of the data storage on the core side.
US09235350B2
A data slice to be stored in a dispersed storage unit of the dispersed storage system is received. A plurality of data blocks are generated from the data slice and metadata are generated associated with each of the plurality of data blocks. A data file is generated based on the plurality of data blocks. A metadata file is generated based on the metadata associated with the plurality of data blocks. The metadata file and the data file are stored in at least one memory of the dispersed storage unit.
US09235347B2
A system, method and computer program product for synchronizing data written to tape with improved data recovery. When writing data to tape, an index is kept in memory and updated to reflect change(s) to a file system mounted on tape. After a predetermined amount of data is written to a tape, a device may perform a sync operation, causing the index to be written into a data partition of the tape. If the sync operation is successful, the index in the index partition of the tape can be updated using a copy of the index in the data partition of the tape next time the tape is mounted. If the sync operation is not successful, the device may write the data to a different location on the same or another tape, update the index, and force another sync operation. This process can be repeated.
US09235342B2
Arrangements described herein relate to sharing a view presented on a touchscreen of a processing system. Whether a show gesture state is enabled on the processing system and whether a gesture event gate is open on the processing system are determined. The show gesture state determines whether a gesture detected by the touchscreen is depicted onto a version of the view shared with another processing system. The gesture event gate determines whether a corresponding gesture event is passed to an application that is active in the view.
US09235341B2
Apparatus, a method and a computer program are provided. The apparatus includes: at least one processor; and at least one memory storing computer program instructions, the at least one processor being configured to execute the computer program instructions to cause the apparatus at least to perform: controlling a touch sensitive display to display a first graphical item at a first position and a second graphical item at a second position, the second graphical item being separated from the first graphical item by a first distance; detecting a first user digit at the first position and a second user digit at the second position; reducing the first distance by moving at least one of the first and second graphical items across the touch sensitive display, in response to detecting movement, across the touch sensitive display, of at least one of the first and second user digits; and controlling the touch sensitive display to display a third graphical item, after determining the first distance has been reduced such that the first graphical item is proximate the second graphical item.
US09235329B2
A system and method of managing applications and event notifications using a cursor-based GUI, wherein the cursor-based GUI is located adjacent to the cursor and provides a user with the ability manage and monitor a plurality of dynamically updated applications, commands and event notifications via a persistent and centralized interface. Since the cursor-based GUI is persistent in nature, the plurality of applications, commands and event notifications can be accessed regardless of the user's computer environment. The user can manage user authentication requirements and other configuration information for the cursor-based GUI.
US09235327B2
A computing device displays a set of graphical user interface (GUI) elements each having a respective transparent portion positioned over all or part of an underlying GUI element, which displays underlying content. Each set of GUI elements includes a respective set of peripherally located menu tabs and each menu tab includes a respective set of icons including a first icon corresponding to the first menu tab of a first GUI element. Each selected icon affects content that is displayed in a corresponding transparent portion, including the underlying content displayed within the underlying GUI element that is within the corresponding transparent portion. The computing device receives input selecting the first icon and in response applies a first modification to the content displayed within a first transparent portion which corresponds to the first GUI element and includes the underlying content that is within the first transparent portion.
US09235326B2
A computer program product is described. The computer program product includes a computer useable storage medium including a computer readable program. The computer readable program includes instructions that, when executed by a processing device within a computer, cause the computer to perform operations. The operations include displaying an attraction icon on a display device, moving the attraction icon relative to a user interface control on the display device. The operations further include moving the user interface control from a first position on the display device to a second position to facilitate manipulation of the user interface control by a user, and restoring the user interface control to the first position in response to completion of the manipulation of the user interface control by the user.
US09235325B2
Systems and methods described herein are directed to persona management within a user's single and unified online identity, including defining a plurality of personas for a single identity, the single identity comprising a plurality of personal attributes, associating each of the defined personas with at least one of the plurality of personal attributes, separating the plurality of personas associated with the single identity based on the at least one of the plurality of personal attributes, selecting one of the personas to use in an online interaction with an online application, and controlling access of the online application to the associated at least one of the personal attributes, based on whether the selected one of the plurality of personas corresponds to the online application.
US09235317B2
In one embodiment, one or more components of a user interface are arranged in a hierarchy of layers. The user interface is presented according to the structure of the hierarchy, with a first component of the user interface presented at a first layer. One or more second component are presented at a second layer, the second components being one or more children of the first component and the second layer being one layer above the first layer.
US09235308B2
An embedded touch control display device is disclosed. The embedded touch control display device includes a first substrate and a second substrate which are set oppositely; an in-plane switching (IPS) or fringe field switching (FFS) display mode display structure and a capacitance touch structure which are set between the first substrate and the second substrate, and the IPS or FFS display mode display structure is located on the first substrate and comprises a pixel electrode layer, a first medium layer, a public electrode layer and a crystal layer, and the capacitance touch structure is located on the second substrate and comprises touch electrode and a second medium layer; an planarization layer which is located between the second medium layer and the crystal layer; the distance between the touch electrode and the crystal layer is 4 micrometers to 7 micrometers.
US09235305B2
A configuration of a coordinate position detection apparatus is provided that provides a sufficient sensitivity even in the case of a larger device. A coordinate position detection apparatus (100) includes: a first sensor electrode (Xi); a first capacitance detector (21) connected with the first sensor electrode (Xi) and including an integration circuit; a second sensor electrode (Yj); a second capacitance detector (22) connected with the second sensor electrode (Yj) and including an integration circuit; a coordinate computing unit (25); and a coordinate pointing device (30). In this coordinate position detection apparatus (100), when it is in a first input mode where the coordinate pointing device (30) inputs a coordinate position, a plurality of first and second capacitance detectors (21) and (22) are configured to detect a signal provided by the coordinate pointing device (30), and the coordinate pointing device (30) performs charging and the plurality of first and second capacitance detectors (21) and (22) perform integration during a unit detection period to measure capacitances. Based on the capacitances, the coordinate computing unit (25) determines the coordinate position.