公开(公告)号：US06401048B2

公开(公告)日：2002-06-04

申请号：US09782828

申请日：2001-02-13

Applicant: Raymond J. Caggiano ,  Charles Colpo ,  Jeffrey A. Hatley ,  W. Peter Soroka ,  Rondell K. Watts

Inventor： Raymond J. Caggiano ,  Charles Colpo ,  Jeffrey A. Hatley ,  W. Peter Soroka ,  Rondell K. Watts

IPC: G01R3104

CPC classification number: H05K1/0268 ,  G01R1/06722 ,  G01R31/2805 ,  H05K3/28

Abstract: According to the preferred embodiments of the present invention, a method of creating and accessing additional test points after circuit board design has been completed is disclosed. The apparatus and methods of the present invention provide test engineers with the ability to leave any circuit interconnections located on the exterior surfaces of a PCB exposed. These exposed circuit interconnections may be identified as access or test points and the apparatus of the present invention is specifically adapted to access, probe, and evaluate these access or test points. To allow the exposed circuit interconnections to be tested without damaging them, the invention includes a new type of probe for use in contacting the exposed traces. The preferred embodiments of the test probe apparatus of the present invention has a relatively flat head to reduce pressure on the circuit interconnections and is coated with dendrites to enhance electrical connectivity between the circuit interconnections and the probe. By using both the apparatus and the methods of the present invention, additional test points may be created on the surface of a PCB after circuit and board design has been completed.

Abstract translation: 根据本发明的优选实施例，公开了在电路板设计完成之后创建和访问附加测试点的方法。 本发明的装置和方法为测试工程师提供了放置在暴露于PCB的外表面上的任何电路互连的能力。 这些暴露的电路互连可以被识别为访问或测试点，并且本发明的装置特别适于访问，探测和评估这些访问或测试点。 为了允许暴露的电路互连测试而不损坏它们，本发明包括用于接触暴露的迹线的新型探针。 本发明的测试探针装置的优选实施例具有相对平坦的头部，以减小电路互连上的压力，并且用枝晶涂覆以增强电路互连和探针之间的电连接性。 通过使用本发明的装置和方法，可以在电路和电路板设计完成之后在PCB的表面上产生额外的测试点。

公开(公告)号：US06498997B1

公开(公告)日：2002-12-24

申请号：US09136303

申请日：1998-08-19

Applicant: Akihiko Takada

Inventor： Akihiko Takada

IPC: G01R3104

CPC classification number: H01L24/85 ,  G01R31/04 ,  G01R31/2831 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/85181 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method and an apparatus for producing a solid actuator employing measurement of the electric characteristic of the actuator and effecting polarization during the wire bonding process. After a wire has been bonded to pads formed on a substrate, the conduction of the wire is tested. Then, whether or not a capacitance between the pads has a preselected value is determined. Subsequently, whether or not a characteristic impedance between the pads has a preselected value is determined. Thereafter, whether or not any crack is present in the surfaces of electrodes electrically connected to the pads is determined. This is followed by the polarization of the substrate. Electrical characteristics are tested after each wire is bonded. There is also provided a storage medium storing a program for controlling the above apparatus.

Abstract translation: 一种用于制造固体致动器的方法和装置，其采用测量致动器的电特性并在引线接合过程中产生极化。 在将导线结合到形成在基板上的焊盘之后，测试导线的导通。 然后，确定焊盘之间的电容是否具有预选值。 随后，确定焊盘之间的特性阻抗是否具有预选值。 此后，确定在电连接到焊盘的电极的表面中是否存在任何裂纹。 其次是基板的极化。 在每根导线接合后测试电气特性。 还提供了一种存储用于控制上述装置的程序的存储介质。

公开(公告)号：US06815962B2

公开(公告)日：2004-11-09

申请号：US10216836

申请日：2002-08-13

Applicant: Takayuki Hirano ,  Yasuji Yoneda ,  Hiroshi Gotoh ,  Eiji Iwamura ,  Susumu Takeuchi

Inventor： Takayuki Hirano ,  Yasuji Yoneda ,  Hiroshi Gotoh ,  Eiji Iwamura ,  Susumu Takeuchi

IPC: G01R3104

CPC classification number: G01R1/07307

Abstract: There is provided an electric connection-inspection device which does not impair a freedom of selection of using materials from a viewpoint of restriction in terms of product's function with the aptitude of electric features of electric resistance and physical properties of internal stress, and restriction in terms of manufacture as to the appropriation or not of employment of a plating method, and which has a fine construction provided with the excellent durability that an electrode element is hard to adhere and coagulate. An electric connection-inspection device for coming into electrically contact with an object to be inspected to input and output a signal, comprising a plurality of contact terminals, a coating of a second layer having the Young's modulus higher than that of a wiring base-material layer and whose specific resistance is not more than 1×10−4 &OHgr;cm being formed on the surface of the wiring base-material layer positioned at the extreme end of the contact terminal, and a coating of a third layer having a low coagulating property being formed on the surface of the second layer.

公开(公告)号：US06188235B1

公开(公告)日：2001-02-13

申请号：US08557039

申请日：1996-01-23

Applicant: Manfred Buks ,  Karim Hosseini

Inventor： Manfred Buks ,  Karim Hosseini

IPC: G01R3104

CPC classification number: G01R31/041

Abstract: A test method for verifying proper connection of a CMOS IC uses measurements of a transistor within the IC which can be done with a conventional transistor tester. The transistor has its base connected to a ground pin of the IC, its collector connected to a signal pin of the IC, and its emitter connected to another signal pin of the IC. A second collector of the transistor is connected to a supply voltage pin. The method uses a first step in which suitable voltages are applied to the emitter, base and first collector to turn the transistor on, whereupon the first collector current and second collector voltage are measured. In a second step, the same voltages are applied to the emitter and base as were applied in the first step and a voltage is applied to the second collector which is equal to the voltage measured there in the first step. In a third step, the first collector current measured in the first step is subtracted from the second collector current of the second step, resulting in the true collector current. Alternatively, the method begins with the same first step as described above and in a second step a voltage equal to that measured at the second collector is applied to the second collector while additional current flowing between the collectors is measured. In a third step, the first collector current from the first step is subtracted from the additional current of the second step to give true collector current.

Abstract translation: 用于验证CMOS IC的正确连接的测试方法使用可以用常规晶体管测试仪完成的IC内的晶体管的测量。 晶体管的基极连接到IC的接地引脚，其集电极连接到IC的信号引脚，其发射极连接到IC的另一个信号引脚。 晶体管的第二集电极连接到电源电压引脚。 该方法使用第一步骤，其中合适的电压施加到发射极，基极和第一集电极以使晶体管导通，由此测量第一集电极电流和第二集电极电压。 在第二步骤中，在第一步骤中施加相同的电压到发射极和基极，并且将电压施加到第二集电极，其等于在第一步骤中测量的电压。 在第三步骤中，从第二步骤的第二集电极电流中减去在第一步骤中测量的第一集电极电流，导致真正的集电极电流。 或者，该方法以与上述相同的第一步骤开始，并且在第二步骤中，将等于在第二收集器处测得的电压的电压施加到第二集电器，同时测量在集电极之间流过的附加电流。 在第三步骤中，从第二步骤的附加电流中减去第一步骤的第一集电极电流，以产生真正的集电极电流。

公开(公告)号：US06681193B2

公开(公告)日：2004-01-20

申请号：US09765502

申请日：2001-01-18

Applicant: Carlo Dallavalle

Inventor： Carlo Dallavalle

IPC: G01R3104

CPC classification number: G01R31/3004 ,  G01R31/3008

Abstract: Testing a CMOS integrated circuit includes establishing a current threshold value, powering the integrated circuit in static and idle conditions, measuring the current absorbed by the integrated circuit and comparing this with the threshold value and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured is respectively lower or higher than the threshold value. To improve discrimination between non-faulty and faulty devices, the threshold value is obtained by forming two measurement transistors in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents. Also, the method includes calculating the sub-threshold currents by channel unit of area of the transistors of the integrated circuit using the sub-threshold currents measured and the channel areas of the measurement transistors, obtaining the sum of the channel areas of the transistors that are cut off when the integrated circuit is idle in static conditions, and calculating the current absorbed by the integrated circuit when idle in static conditions using the result of the two operations described above and adding a pre-established current increase to the current absorbed to obtain the threshold value.

Abstract translation: 测试CMOS集成电路包括建立电流阈值，为静态和空闲状态下的集成电路供电，测量集成电路吸收的电流，并将其与阈值进行比较，并接受或拒绝集成电路，如果比较显示 电流吸收测量值分别低于或高于阈值。 为了改善非故障和故障设备之间的区分，阈值通过在集成电路中形成两个测量晶体管，一个n沟道和另一个p沟道，将其偏置在截止区域中并测量其次阈值电流 。 此外，该方法包括使用所测量的子阈值电流和测量晶体管的沟道面积来计算子阈值电流，通过集成电路的晶体管的面积的通道单位，获得晶体管的沟道区域之和， 在静态条件下，当集成电路处于空闲状态时被切断，并且使用上述两种操作的结果计算在静态条件下空闲时由集成电路吸收的电流，并将预先建立的电流增加与吸收的电流相加，以获得 阈值。

公开(公告)号：US06391669B1

公开(公告)日：2002-05-21

申请号：US09598426

申请日：2000-06-21

Applicant: Benjamin V. Fasano ,  Hai P. Longworth ,  Vincent P. Peterson, III ,  Anthony L. Plachy ,  Robert N. Wiggin

Inventor： Benjamin V. Fasano ,  Hai P. Longworth ,  Vincent P. Peterson, III ,  Anthony L. Plachy ,  Robert N. Wiggin

IPC: G01R3104

CPC classification number: H01L22/34 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  H05K1/116 ,  H05K3/1225 ,  H05K3/4061 ,  H05K3/4614 ,  H05K3/4638 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2203/166 ,  Y10T29/49004

Abstract: Multilayer substrates, are fabricated with the incorporation therein of non-destructive test structures utilized to provide visual and electrical test data to facilitate the ascertainment and assessment of potential electrical interface failures. Furthermore, there are provided embedded structures in multilayer substrates, such as are employed in chip carrier packaging, so as to facilitate electrical testing for via to via alignment and interface layer alignment, and to enable the testing of conductive interface electrical integrity of multilayer electrical devices.

Abstract translation: 制造多层基板，其中结合有非破坏性测试结构，用于提供视觉和电气测试数据，以便于确定和评估潜在的电接口故障。 此外，在多层基板中提供了嵌入式结构，例如用于芯片载体封装，以便于通孔经由对准和界面层对准的电气测试，并且能够测试多层电气设备的导电界面电气完整性 。

公开(公告)号：US06356852B1

公开(公告)日：2002-03-12

申请号：US09368029

申请日：1999-08-03

Applicant: Meng-Kun Ke

Inventor： Meng-Kun Ke

IPC: G01R3104

CPC classification number: G01R27/28

Abstract: A multi-port programmable analog tester for testing an analog device having more than two test ports includes a two-port network analyzer having two network analyzer ports and an interface device coupled to the network analyzer. The interface device has at least two levels of switches, and is adapted to be coupled to the test ports of the analog device.

Abstract translation: 用于测试具有两个以上测试端口的模拟设备的多端口可编程模拟测试器包括具有两个网络分析器端口的双端口网络分析器和耦合到网络分析器的接口设备。 接口设备具有至少两个级别的开关，并且适于耦合到模拟设备的测试端口。