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公开(公告)号:US20240204982A1
公开(公告)日:2024-06-20
申请号:US18594822
申请日:2024-03-04
发明人: Nitzan DROR
CPC分类号: H04L7/0033 , H04J3/0685
摘要: A physical layer (PHY) processor of a network device receives a timing message via an external network and generates a first timestamp using a first local-domain clock used by the
PHY processor. The PHY processor transfers the timing message and the first timestamp to a packet processor of the network device via an internal communication link. The packet processor generates a second timestamp for the timing message using a domain-specific clock. The packet processor determines a delay value using the first timestamp, the delay value accounting for a time delay corresponding to the transfer of the timing message within the network device from the PHY processor to the packet processor. The packet processor adjusts the second timestamp using the delay value to generate an adjusted domain-specific timestamp for the timing message.-
公开(公告)号:US11979314B2
公开(公告)日:2024-05-07
申请号:US18078727
申请日:2022-12-09
发明人: Ilan Yerushalmi , Adar Peery , David Melman
IPC分类号: G06F15/16 , H04L45/02 , H04L45/24 , H04L45/745
CPC分类号: H04L45/24 , H04L45/04 , H04L45/745
摘要: A network device includes a plurality of network interfaces configured to couple with a plurality of physical network links. A packet processor is configured to process packets received via the plurality of network interfaces. The packet processor includes a path selection engine that is configured to: for each of at least some packets processed by the packet processor, successively make path selection decisions that correspond to respective routing domains within a hierarchical communication network, the path selection decisions for forwarding the packet through the hierarchical communication network.
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公开(公告)号:US20240098042A1
公开(公告)日:2024-03-21
申请号:US18514652
申请日:2023-11-20
发明人: David MELMAN , Ilan MAYER-WOLF , Carmi ARAD , Rami ZEMACH
IPC分类号: H04L49/90 , H04L47/2441 , H04L47/32 , H04L69/22
CPC分类号: H04L49/9084 , H04L47/2441 , H04L47/32 , H04L69/22
摘要: A network device includes a receive processor configured to store, in a packet memory, a payload of a packet received from a communication network. The network device also includes a packet processor configured to modify one or more fields of a header of the packet to generate a modified header, perform egress classification of the packet based on the modified header, and store the modified header in the packet memory. The network device further includes a transmit processor configured to transmit the packet in accordance with the egress classification. The transmit processor is configured to, in response to a decision that the packet is to be transmitted from the network device, generate a transmit packet from the payload retrieved from the packet memory and the modified header retrieved from the packet memory and cause the transmit packet to be transmitted to a destination in the communication network.
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公开(公告)号:US11929931B2
公开(公告)日:2024-03-12
申请号:US17972000
申请日:2022-10-24
IPC分类号: H04L47/122 , H04L47/33 , H04L47/52 , H04L47/722 , H04L49/90
CPC分类号: H04L47/122 , H04L47/33 , H04L47/521 , H04L47/722 , H04L49/9078
摘要: A packet processor of a network device receives packets ingressing from a plurality of network links via a plurality of network ports of the network device. The packet processor buffers the packets in an internal packet memory in a plurality of queues, including a first queue. In response to the packet processor detecting congestion in the internal packet memory, the packet processor selectively forwards a group of multiple packets in the first queue from the internal packet memory to a first port, among one or more ports coupled to one or more external memories, to transfer the group of multiple packets to a first external memory that is coupled to the first port so that the first queue is stored across the internal packet memory and the first external packet memory.
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公开(公告)号:US11916795B2
公开(公告)日:2024-02-27
申请号:US17318076
申请日:2021-05-12
发明人: Tal Mizrahi , David Melman
IPC分类号: H04L47/2441 , H04L69/22 , H04L45/74
CPC分类号: H04L47/2441 , H04L45/74 , H04L69/22
摘要: Methods and systems are provided for processing a received packet based on associated state information. A packet processor of a network device receives a packet from a network. The received packet is classified as belonging to at least one respective identified flow from among a plurality of identified flows. For a respective received packet that belongs to an identified flow a current state value for the identified flow is ascertained based on a state table. The current state value is assigned to the respective received packet based on the current state value using the state table for the identified flow. A packet processing operation is subsequently performed on the respective received packet based in part on the state value of the identified flow to which the respective packet belongs.
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公开(公告)号:US11581292B2
公开(公告)日:2023-02-14
申请号:US16898261
申请日:2020-06-10
发明人: Dan Azeroual , Liav Ben Artsi
摘要: A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.
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公开(公告)号:US11508663B2
公开(公告)日:2022-11-22
申请号:US16260732
申请日:2019-01-29
发明人: Dan Azeroual , Eldad Bar-Lev
摘要: Aspects of the disclosure provide a printed circuit board (PCB) system that includes an integrated circuit (IC) package, a first PCB and a PCB module. The IC package has a package substrate and an IC chip that is coupled to a top surface of the package substrate. The first PCB is configured to electrically couple with first contact structures that are disposed on a bottom surface of the package substrate. The PCB module includes a second PCB and one or more electronic components electrically coupled to the second PCB. The PCB module is configured to electrically couple with second contact structures that are disposed on the top surface of the package substrate.
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公开(公告)号:US20210352024A1
公开(公告)日:2021-11-11
申请号:US17383601
申请日:2021-07-23
发明人: David MELMAN , Ilan MAYER-WOLF , Carmi ARAD , Rami ZEMACH
IPC分类号: H04L12/861 , H04L12/851 , H04L12/823 , H04L29/06
摘要: A network device includes a packet processor that: determines at least one egress port via which a received packet is to be transmitted by the network device; modifies one or more fields in a header of the packet to generate a modified header; determines, based at least in part on the modified header, whether the packet a) is to be transmitted or b) is to be discarded; and stores the modified header in a packet memory. In response to the determination that the packet is to be transmitted, a transmit processor of the network device: retrieves a payload of the packet from the packet memory; retrieves the modified header from the packet memory; generates a transmit packet at least by combining the payload of the packet with the modified header; and transmits the transmit packet via the determined at least one egress port of the network device.
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公开(公告)号:US11057136B1
公开(公告)日:2021-07-06
申请号:US16594781
申请日:2019-10-07
发明人: Tal Mizrahi
摘要: A network device receives a packet that conforms to a protocol that i) defines a time stamp field, ii) does not define a dedicated field for time correction information, and iii) defines a plurality of general purpose extension fields. The packet includes (i) a time stamp generated by a source node in the time stamp field, and (ii) a time correction value corresponding to multiple ones of the plurality of intermediate nodes, the time correction value being located in one of the general purpose extension fields. The network device identifies (i) a time specified by the time stamp, and (ii) time correction information specified in the one general purpose extension field, and uses the time correction information and the time specified by the time stamp to synchronize a clock maintained by the network device to a clock maintained by the source node.
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公开(公告)号:US20210160184A1
公开(公告)日:2021-05-27
申请号:US16829939
申请日:2020-03-25
发明人: Yosef KATAN , Rami ZEMACH
IPC分类号: H04L12/803
摘要: Flow state information that is stored in a first memory among a plurality of memories for maintaining flow state information at a network device is updated based on packets ingressing the network device. The memories are arranged in a hierarchical arrangement in which memories at progressively higher levels of hierarchy are configured to maintain flow state information corresponding to progressively larger sets of flows processed by the network device. When it is determined that a fullness level of the first memory exceeds a first threshold, flow state information associated with at least one flow, among a first set of flows for which flow state information is currently being maintained in the first memory, is transferred from the first memory to a second memory, the second memory being at a higher hierarchical level than the first memory. A new flow is instantiated in space freed up in the first memory.
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