公开(公告)号：US20100225507A1

公开(公告)日：2010-09-09

申请号：US12712249

申请日：2010-02-25

Applicant: Yasuyuki Shirasaka ,  Norikazu Okada

Inventor： Yasuyuki Shirasaka ,  Norikazu Okada

IPC: H03M5/02

CPC classification number: G01P3/489 ,  G01D5/36 ,  G01P13/045 ,  H03M5/20

Abstract: A decoder device has a reference voltage generating section for outputting first and second threshold level signals, a first comparator for comparing a stair-stepped waveform input signal and the first threshold level signal to output a comparison result, a second comparator for comparing the input signal and the second threshold level signal to output a comparison result, and a logical operation section for performing a logical operation between output signals of the first and second comparators to output a signal decoded from the input signal. A threshold level represented by the first threshold level signal intersects a riser section of one stepped waveform out of two adjacent stepped waveforms in the input signal, and a threshold level represented by the second threshold level signal intersects a riser section of the other stepped waveform out of the two adjacent stepped waveforms of the stair-stepped waveform input signal.

Abstract translation: 解码器装置具有用于输出第一和第二阈值电平信号的参考电压产生部分，用于比较阶梯式波形输入信号和第一阈值电平信号以输出比较结果的第一比较器，用于比较输入信号 和第二阈值电平信号以输出比较结果，以及逻辑运算部分，用于在第一和第二比较器的输出信号之间执行逻辑运算，以输出从输入信号解码的信号。 由第一阈值电平信号表示的阈值电平与输入信号中的两个相邻阶梯波形中的一个阶梯波形的提升部分相交，并且由第二阈值电平信号表示的阈值电平与另一阶梯波形输出的提升部分相交 的台阶阶波形输入信号的两个相邻阶梯波形。

公开(公告)号：US08040267B2

公开(公告)日：2011-10-18

申请号：US12712249

申请日：2010-02-25

Applicant: Yasuyuki Shirasaka ,  Norikazu Okada

Inventor： Yasuyuki Shirasaka ,  Norikazu Okada

IPC: H03M1/12

CPC classification number: G01P3/489 ,  G01D5/36 ,  G01P13/045 ,  H03M5/20

Abstract: A decoder device has a reference voltage generating section for outputting first and second threshold level signals, a first comparator for comparing a stair-stepped waveform input signal and the first threshold level signal to output a comparison result, a second comparator for comparing the input signal and the second threshold level signal to output a comparison result, and a logical operation section for performing a logical operation between output signals of the first and second comparators to output a signal decoded from the input signal. A threshold level represented by the first threshold level signal intersects a riser section of one stepped waveform out of two adjacent stepped waveforms in the input signal, and a threshold level represented by the second threshold level signal intersects a riser section of the other stepped waveform out of the two adjacent stepped waveforms of the stair-stepped waveform input signal.

Abstract translation: 解码器装置具有用于输出第一和第二阈值电平信号的参考电压产生部分，用于比较阶梯式波形输入信号和第一阈值电平信号以输出比较结果的第一比较器，用于比较输入信号 和第二阈值电平信号以输出比较结果，以及逻辑运算部分，用于在第一和第二比较器的输出信号之间执行逻辑运算，以输出从输入信号解码的信号。 由第一阈值电平信号表示的阈值电平与输入信号中的两个相邻阶梯波形中的一个阶梯波形的提升部分相交，并且由第二阈值电平信号表示的阈值电平与另一阶梯波形输出的提升部分相交 的台阶阶波形输入信号的两个相邻阶梯波形。

公开(公告)号：US08664580B2

公开(公告)日：2014-03-04

申请号：US13402225

申请日：2012-02-22

Applicant: Kohei Yasukawa ,  Norikazu Okada ,  Yasuyuki Shirasaka

Inventor： Kohei Yasukawa ,  Norikazu Okada ,  Yasuyuki Shirasaka

IPC: H01J40/14

CPC classification number: G01J1/44

Abstract: The optical sensor includes a photodiode PD1 with its anode grounded, a diode group DG1 having one end connected to a cathode of the photodiode PD1, a current source I1 having one end connected to the other end of the diode group DG1, a power supply section for applying a constant voltage to the other end of the current source I1, and a grounded-emitter NPN transistor QOUT1 having a base connected to the cathode of the photodiode PD1 and a collector connected to one end of the current source I1. The diode group DG1 is provided by n diodes D1, D2, . . . , Dn connected in series so that their forward directions are directed toward the photodiode PD1 side, and a photocurrent which flows from a connecting point between the diode group and the current source to the photodiode is converted into a voltage and outputted as a photoelectric conversion signal.

Abstract translation: 光传感器包括其阳极接地的光电二极管PD1，一端连接到光电二极管PD1的阴极的二极管组DG1，一端连接到二极管组DG1的另一端的电流源I1，电源部分 用于向电流源I1的另一端施加恒定电压，以及具有连接到光电二极管PD1的阴极的基极的接地发射极NPN晶体管QOUT1和连接到电流源I1的一端的集电极。 二极管组DG1由n个二极管D1，D2提供。 。 。 ，Dn串联连接，使其正向指向光电二极管PD1侧，从二极管组和电流源之间的连接点流向光电二极管的光电流转换为电压并作为光电转换信号输出 。

公开(公告)号：US20120211639A1

公开(公告)日：2012-08-23

申请号：US13402225

申请日：2012-02-22

Applicant: Kohei YASUKAWA ,  Norikazu Okada ,  Yasuyuki Shirasaka

Inventor： Kohei YASUKAWA ,  Norikazu Okada ,  Yasuyuki Shirasaka

IPC: G01J1/44

CPC classification number: G01J1/44

Abstract: The optical sensor includes a photodiode PD1 with its anode grounded, a diode group DG1 having one end connected to a cathode of the photodiode PD1, a current source I1 having one end connected to the other end of the diode group DG1, a power supply section for applying a constant voltage to the other end of the current source I1, and a grounded-emitter NPN transistor QOUT1 having a base connected to the cathode of the photodiode PD1 and a collector connected to one end of the current source I1. The diode group DG1 is provided by n diodes D1, D2, . . . , Dn connected in series so that their forward directions are directed toward the photodiode PD1 side, and a photocurrent which flows from a connecting point between the diode group and the current source to the photodiode is converted into a voltage and outputted as a photoelectric conversion signal.

Abstract translation: 光传感器包括其阳极接地的光电二极管PD1，一端连接到光电二极管PD1的阴极的二极管组DG1，一端连接到二极管组DG1的另一端的电流源I1，电源部分 用于向电流源I1的另一端施加恒定电压，以及具有连接到光电二极管PD1的阴极的基极的接地发射极NPN晶体管QOUT1和连接到电流源I1的一端的集电极。 二极管组DG1由n个二极管D1，D2提供。 。 。 ，Dn串联连接，使其正向指向光电二极管PD1侧，从二极管组和电流源之间的连接点流向光电二极管的光电流转换为电压并作为光电转换信号输出 。

公开(公告)号：US07321530B2

公开(公告)日：2008-01-22

申请号：US10830213

申请日：2004-04-21

Applicant: Katsuyuki Kawamura ,  Yasuyuki Shirasaka

Inventor： Katsuyuki Kawamura ,  Yasuyuki Shirasaka

IPC: G11B7/00

CPC classification number: G11B7/13

Abstract: A decoder circuit of the present invention, mounted on an integrated circuit, decodes input voltage Vin supplied to a single external input terminal into three or more control outputs, and an object of the present invention is to reduce the size of a chip. The foregoing decoder circuit includes: a P-type transistor in which an emitter is connected to a power source line of high level, a base is connected to the external input terminal, and a collector is an output terminal of a first control output; and an N-type transistor in which an emitter is connected to a power source line of low level, a base is connected to the external input terminal, and a collector is an output terminal of a second control output, and decodes the control outputs to three or more sets of data by carrying out logic operations. Therefore, as compared to the case of using a comparator requiring many transistors, a constant current source, and other elements, one each transistor is required for each of the two control outputs to be generated. This facilitates size reduction of a chip.

Abstract translation: 安装在集成电路上的本发明的解码器电路将提供给单个外部输入端的输入电压Vin解码为三个或更多个控制输出，本发明的目的是减小芯片的尺寸。 上述解码器电路包括：P型晶体管，其中发射极连接到高电平电源线，基极连接到外部输入端，集电极是第一控制输出的输出端; 以及N型晶体管，其中发射极连接到低电平电源线，基极连接到外部输入端，集电极是第二控制输出的输出端，并将控制输出解码为 通过执行逻辑操作三个或更多组数据。 因此，与使用需要许多晶体管，恒定电流源和其它元件的比较器的情况相比，要产生两个控制输出中的每一个需要一个晶体管。 这有助于芯片的尺寸减小。