公开(公告)号：US10289784B1

公开(公告)日：2019-05-14

申请号：US15432537

申请日：2017-02-14

Applicant: Xilinx, Inc.

Inventor： Chiao K. Hwang ,  Zicheng G. Ling ,  Nagaraj Savithri

IPC: G06F17/50

Abstract: The disclosed approaches process a circuit design that specifies a clock signal. A plurality of wire segments of an integrated circuit (IC) are selected for a clock path to carry the clock signal. A delay of the clock path is determined based on delay values associated with identifiers of the wire segments and variation factors. Configuration data is generated from the circuit design once the delay of the clock path satisfies a timing constraint, and a circuit is generated from the configuration data to implement a circuit according to the circuit design.