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    Visualizing transactions of a transaction-based system
    3.
    发明授权
    Visualizing transactions of a transaction-based system 有权

    公开(公告)号：US09626780B1

    公开(公告)日：2017-04-18

    申请号：US14312616

    申请日：2014-06-23

    Applicant: Xilinx, Inc.

    Inventor： Yi-Hua E. Yang ,  Patrick Lysaght ,  Paul R. Schumacher ,  Graham F. Schelle

    IPC: G06T11/20

    CPC classification number: G06T11/206 ,  G06T11/203

    Abstract: Visualizing transactions in a transaction-based system includes displaying, on a display device, an x-y coordinate system including an x-axis and a y-axis, wherein the x-axis is demarcated in units of time and the y-axis is demarcated according to a transaction characteristic and formatting, using a processor, each of a plurality of transactions of a transaction system as a line having a start end representing a start of the transaction and a terminating end representing an end of the transaction. For each line representing a transaction, the start end of the line is located at a first x-coordinate corresponding to a start time of the transaction and a first y-coordinate of zero. For each line, the terminating end of the line is located at a second x-coordinate corresponding to an end time of the transaction and a second non-zero y-coordinate that is the same for each line. Each line is displayed on the display device using the processor in combination with the x-y coordinate system.

    Integrated circuit pre-boot metadata transfer
    4.
    发明授权
    Integrated circuit pre-boot metadata transfer 有权
    集成电路预引导元数据传输

    公开(公告)号：US09323876B1

    公开(公告)日：2016-04-26

    申请号：US14552321

    申请日：2014-11-24

    Applicant: Xilinx, Inc.

    Inventor： Patrick Lysaght ,  Yi-Hua E. Yang ,  Paul R. Schumacher ,  Graham F. Schelle

    IPC: G06F17/50 ,  G06F9/445

    CPC classification number: G06F8/65 ,  G06F17/5054

    Abstract: Pre-boot metadata transfer may include loading a first configuration bitstream into a programmable integrated circuit (IC), wherein the first configuration bitstream includes a first circuit design and metadata for a second circuit design. The metadata may be stored within a memory of the programmable IC. A configuration bitstream load condition may be detected and, responsive to the configuration bitstream load condition, a second configuration bitstream may be loaded into the programmable IC. The second configuration bitstream includes a second circuit design.

    Abstract translation: 预引导元数据传输可以包括将第一配置比特流加载到可编程集成电路（IC）中，其中第一配置比特流包括用于第二电路设计的第一电路设计和元数据。 元数据可以存储在可编程IC的存储器中。 可以检测配置比特流加载条件，并且响应于配置比特流加载条件，可以将第二配置比特流加载到可编程IC中。 第二配置比特流包括第二电路设计。

    Active interrupt handler performance monitoring in microprocessors
    5.
    发明授权
    Active interrupt handler performance monitoring in microprocessors 有权

    公开(公告)号：US10282326B1

    公开(公告)日：2019-05-07

    申请号：US14527659

    申请日：2014-10-29

    Applicant: Xilinx, Inc.

    Inventor： Yi-Hua E. Yang ,  Patrick Lysaght ,  Austin H. Lesea ,  Graham F. Schelle ,  Paul R. Schumacher

    IPC: G06F13/24 ,  G06F13/26

    Abstract: An integrated circuit is provided for obtaining interrupt performance metrics. The integrated circuit includes a microprocessor executing an interrupt service routing monitoring framework that includes an interrupt handler and an application programming interface. The interrupt handler executes in response to a trigger condition and obtains timing data that includes at least one sample of a value of a timing logic according to a sampling schedule. The API exposes interrupt configuration functionality for registering the interrupt handler with a supervisory program and for configuring the interrupt handler to obtain the timing data.

    Intelligent and adaptive benchmark testing framework
    6.
    发明授权
    Intelligent and adaptive benchmark testing framework 有权

    公开(公告)号：US09983971B1

    公开(公告)日：2018-05-29

    申请号：US14713814

    申请日：2015-05-15

    Applicant: Xilinx, Inc.

    Inventor： Yi-Hua E. Yang ,  Patrick Lysaght

    IPC: G21C17/00 ,  G06F11/34 ,  G06F11/30

    CPC classification number: G06F11/3428

    Abstract: Techniques for efficient benchmarking. One method includes obtaining convergent results by performing a benchmarking test with a particular length to obtain a result (time), scaling the time exponentially, performing additional benchmarking tests, obtaining results for those tests, and determining whether the results scale linearly with length. Another method includes obtaining variance for non-convergent results by performing multiple sequences of benchmarking test. Within each new sequence performed, the benchmarking tests are spaced out further apart in time. If new maximum or minimum results are obtained, then further test sequences are performed and if no new maximum or minimum results are obtained after a threshold number of sequences, then the test ends. A device and computer-readable medium for performing benchmarking are also provided herein.

    Methods and circuits for testing partial circuit designs
    7.
    发明授权
    Methods and circuits for testing partial circuit designs 有权
    用于测试部分电路设计的方法和电路

    公开(公告)号：US09581643B1

    公开(公告)日：2017-02-28

    申请号：US14924131

    申请日：2015-10-27

    Applicant: Xilinx, Inc.

    Inventor： Graham F. Schelle ,  Yi-Hua E. Yang ,  Paul R. Schumacher ,  Patrick Lysaght

    IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

    CPC classification number: G06F17/5022

    Abstract: Methods and circuits are disclosed for testing a partial circuit design including circuit modules having a set of ports configured to be driven by signals from ports of one or more circuits omitted from the partial circuit. The set of ports are identified by identifying ports that are not connected by a net to another port or input/output (I/O) pin in the circuit design and that form inputs to slave circuits in the circuit modules. A traffic generator circuit is added to the partial design to form a test circuit design. The traffic generator circuit is configured to provide to the set of ports respective input data signals having a pattern consistent with master-to-slave communication. Operation of a test circuit design is modeled. A set of data signals generated by the circuit modules during the modeled operation of the test circuit design is captured and stored.

    Abstract translation: 公开了用于测试部分电路设计的方法和电路，其包括具有一组端口的电路模块，该端口被配置为由来自部分电路省略的一个或多个电路的端口的信号驱动。 通过识别端口不被网络连接到电路设计中的另一个端口或输入/输出（I / O）引脚，并在电路模块中形成输入到从电路的端口。 交通发电机电路被添加到部分设计中以形成测试电路设计。 业务发生器电路被配置为向该组端口提供具有与主从通信一致的模式的相应输入数据信号。 测试电路设计的运行被建模。 捕获并存储在测试电路设计的建模操作期间由电路模块产生的一组数据信号。

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