公开(公告)号：US09613173B1

公开(公告)日：2017-04-04

申请号：US14873072

申请日：2015-10-01

Applicant: Xilinx, Inc.

Inventor： Rajat Aggarwal ,  Zhiyong Wang ,  Ruibing Lu ,  Sabyasachi Das

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

公开(公告)号：US20170098024A1

公开(公告)日：2017-04-06

申请号：US14873072

申请日：2015-10-01

Applicant: Xilinx, Inc.

Inventor： Rajat Aggarwal ,  Zhiyong Wang ,  Ruibing Lu ,  Sabyasachi Das

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.