公开(公告)号：US10540463B1

公开(公告)日：2020-01-21

申请号：US15895737

申请日：2018-02-13

Applicant: Xilinx, Inc.

Inventor： Maheshwar Chandrasekar ,  Sabyasachi Das

IPC: G06F17/50 ,  H03K19/177 ,  H01L21/822

Abstract: Disclosed approaches for processing a circuit design include identifying a driver and a load having a hold violation in the circuit design. The circuit design is targeted to an integrated circuit (IC) die. The method determines a first offset from a location on a perimeter of a rectangular region of the IC die having corners at locations of the driver and the load such that a length of a signal path from the driver through a first candidate location having placement coordinates that are outside the rectangular region and at the first offset from the location on the perimeter resolves the hold violation. The method determines availability of the first candidate location. In response to determining that the first candidate location is available, the method includes instantiating a delay circuit at the first candidate location and specifying connections that connect the delay circuit between the driver and the load.