公开(公告)号：US10288496B1

公开(公告)日：2019-05-14

申请号：US15236703

申请日：2016-08-15

Applicant: Xilinx, Inc.

Inventor： James D. Wesselkamper ,  Frank C. Wirtz, II ,  Giulio Corradi ,  Jason J. Moore

IPC: G01K1/14 ,  G01K13/00 ,  G01R19/25

Abstract: Methods and circuits are disclosed for measuring temperature and/or voltage using ring oscillators. In an example implementation, temperature and/or voltage are determined using an iterative measurements of a ring oscillator. The ring oscillator oscillates with a different voltage-temperature response in each of the first, second and third modes. In each iteration, a first set of indications of frequency are determined for a ring oscillator in a first mode, a second mode, and a third mode. A coarse temperature estimate and a coarse voltage estimate of the ring oscillator are determined based on the indications of frequency measured in a first iteration. A more accurate temperature estimate and a more accurate voltage estimate of the ring oscillator are determined as a function of a second set of indications of frequency measured in a second iteration, the coarse temperature estimate, and the coarse voltage estimate.

公开(公告)号：US10754760B1

公开(公告)日：2020-08-25

申请号：US15982698

申请日：2018-05-17

Applicant: Xilinx, Inc.

Inventor： Paul S. Levy ,  Giulio Corradi

IPC: G06F11/36 ,  G01R31/317

Abstract: Disclosed approaches involve at least one processor executing a program and a debug interface circuit coupled to the processor. The debug interface circuit is configured to transmit first trace data from the first processor. A debug access port is coupled to the debug interface circuit. A fault detection circuit is coupled to the debug access port and is configured to receive the first trace data via the debug access port and compare the first trace data to second data. The fault detection circuit generates an error signal to the first processor in response to a discrepancy between the first trace data and the second data.

公开(公告)号：US20160203096A1

公开(公告)日：2016-07-14

申请号：US14595140

申请日：2015-01-12

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Giulio Corradi

IPC: G06F13/40 ,  G06F13/28

CPC classification number: G06F13/4068 ,  G06F13/28

Abstract: In an example, a programmable integrated circuit (IC) includes programmable logic, a processing system, and a network controller. The network controller includes a media access control unit (MAC), a first interface to a physical transceiver, a second interface to the processing system, and a third interface between the MAC and the programmable logic.

Abstract translation: 在一个示例中，可编程集成电路（IC）包括可编程逻辑，处理系统和网络控制器。 网络控制器包括媒体访问控制单元（MAC），到物理收发器的第一接口，到处理系统的第二接口以及MAC与可编程逻辑之间的第三接口。

公开(公告)号：US09378102B1

公开(公告)日：2016-06-28

申请号：US14452858

申请日：2014-08-06

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Bradley L. Taylor ,  Giulio Corradi

IPC: G06F11/07 ,  G06F11/20 ,  H03K19/177 ,  H03K19/007

CPC classification number: G06F11/2007 ,  H03K19/007 ,  H03K19/17764

Abstract: A system on a chip (SoC) for providing safety hardware fault tolerance and/or safety software fault tolerance includes a first safety sub-system having a first safety channel; a second safety sub-system having a second safety channel; and a third sub-system. The first safety sub-system is independent of the second safety sub-system to allow the second safety sub-system to communicate through the second safety channel when the first safety sub-system or the third subsystem fails, and further to allow the first safety sub-system to communicate through the first safety channel when the second safety sub-system or the third subsystem fails.

Abstract translation: 用于提供安全硬件容错和/或安全软件容错的芯片系统（SoC）包括具有第一安全通道的第一安全子系统; 具有第二安全通道的第二安全子系统; 和第三个子系统。 第一安全子系统独立于第二安全子系统，以允许第二安全子系统在第一安全子系统或第三子系统失效时通过第二安全通道进行通信，并且还允许第一安全子系统 子系统在第二安全子系统或第三子系统出现故障时通过第一安全通道进行通信。

公开(公告)号：US09934185B2

公开(公告)日：2018-04-03

申请号：US14595140

申请日：2015-01-12

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Giulio Corradi

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00 ,  G06F13/28

CPC classification number: G06F13/4068 ,  G06F13/28

Abstract: In an example, a programmable integrated circuit (IC) includes programmable logic, a processing system, and a network controller. The network controller includes a media access control unit (MAC), a first interface to a physical transceiver, a second interface to the processing system, and a third interface between the MAC and the programmable logic.

公开(公告)号：US09772897B1

公开(公告)日：2017-09-26

申请号：US14576771

申请日：2014-12-19

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Giulio Corradi

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/16

Abstract: A processing subsystem for providing diagnostic of a processing system is provided. The processing subsystem includes a real-time processing unit that receives a first input that includes data from one or more sensors and processes the first input to generate first output that controls an actuator. The processing subsystem also includes a power and safety management unit that receives a second input and processes the second input to generate second output for testing of the first output. A method and a system for providing diagnostic for a processing system are provided as well.