公开(公告)号：US20240193227A1

公开(公告)日：2024-06-13

申请号：US18076602

申请日：2022-12-07

Applicant: Xilinx, Inc.

Inventor： Abhishek Kumar Jain ,  Dinesh Gaitonde

IPC: G06F17/16 ,  G06F7/50 ,  G06F7/523 ,  G06F7/544

CPC classification number: G06F17/16 ,  G06F7/50 ,  G06F7/523 ,  G06F7/5443

Abstract: Partition-level compression of an m×n sparse matrix includes determining in each partition, row and column indices of elements having non-zero values. Each partition has s rows and t columns and s

公开(公告)号：US11263169B2

公开(公告)日：2022-03-01

申请号：US17099587

申请日：2020-11-16

Applicant: XILINX, INC.

Inventor： Ian Andrew Swarbrick ,  Sagheer Ahmad ,  Ygal Arbel ,  Dinesh Gaitonde

IPC: G06F11/22 ,  G06F7/50 ,  G06F15/78 ,  H04L41/0813 ,  H04L49/109 ,  G06F13/42 ,  H04L12/40 ,  H04L45/42 ,  H04L45/60

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

公开(公告)号：US10977404B1

公开(公告)日：2021-04-13

申请号：US16775016

申请日：2020-01-28

Applicant: Xilinx, Inc.

Inventor： Srinivas T. Reddy ,  Dinesh Gaitonde ,  Ritesh Mani

IPC: G06F30/347 ,  G01R31/3177

Abstract: Disclosed approaches for dynamically creating one or more scan chains in a programmable integrated circuit (IC) include placing elements of a circuit design on first registers of the programmable IC. A processor can determine second registers of the programmable IC that are unused by the circuit design after placing the elements of the circuit design. Data-out pins of the first registers are coupled to data-in pins of the second registers, respectively, and the second registers are coupled into a scan chain.

公开(公告)号：US20230267169A1

公开(公告)日：2023-08-24

申请号：US17679887

申请日：2022-02-24

Applicant: Xilinx, Inc.

Inventor： Abhishek Kumar Jain ,  Dinesh Gaitonde

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Circuitry for multiplying a sparse matrix by a dense vector includes a first switching circuit (302) for routing input triplets from N input ports to N output ports based on column indices of the triplets. Each triplet includes a non-zero value, a row index, and a column index. N first memory banks (303) store subsets of vector elements and are addressed by the column indices of the triplets. N multipliers (305) multiply the non-zero values of the triplets by the vector element read from the respective memory bank. A second switching circuit (304) routes tuples based on row indices of the tuples. Each tuple includes a product output by the one of the N multipliers and a row index output by an output port of the first switching circuit. N accumulator circuits (307) sum products of tuples having equal row indices.