公开(公告)号：US10482129B1

公开(公告)日：2019-11-19

申请号：US15484455

申请日：2017-04-11

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Ling Liu ,  Daniel Ziener ,  Kimon Karras

IPC: G06F7/02 ,  G06F16/00 ,  G06F16/9038 ,  G06F3/06 ,  G06F16/93 ,  G06F16/901 ,  G06F16/903

Abstract: Disclosed approaches for accessing data involve determining in a first stage of a pipelined processing circuit, hash values from keys in a data access request and determining in a second stage of the pipelined processing circuit and from a hash table, addresses associated with the hash values. In a third stage of the pipelined processing circuit, data are read at the addresses in a memory arrangement, and in a fourth stage of the pipelined processing circuit a subset of the data read from the memory arrangement is selected according to a query in the data access request. In a fifth stage of the pipelined processing circuit, the subset of the data read from the memory arrangement is merged into response data.