公开(公告)号：US20230352623A1

公开(公告)日：2023-11-02

申请号：US18216575

申请日：2023-06-29

Applicant: XIAMEN CHANGELIGHT CO., LTD.

Inventor： Zhiwei LIN ,  Kaixuan CHEN ,  Jianjiu CAI ,  Xiangjing ZHUO ,  Gang YAO ,  Wei CHENG

IPC: H01L33/14 ,  H01L33/04 ,  H01L33/32

CPC classification number: H01L33/145 ,  H01L33/04 ,  H01L33/32

Abstract: The present disclosure provides a semiconductor epitaxial structure and a manufacturing method therefor, and an LED chip. The semiconductor epitaxial structure may include a substrate, an N-type semiconductor layer, a gate elimination layer, an active layer and a P-type semiconductor layer are sequentially stacked on a surface of a substrate. Furthermore, the gate elimination layer comprises an N-type doped semiconductor layer.

公开(公告)号：US20230361245A1

公开(公告)日：2023-11-09

申请号：US18219035

申请日：2023-07-06

Applicant: XIAMEN CHANGELIGHT CO., LTD.

Inventor： Zhiwei LIN ,  Kaixuan CHEN ,  Jianjiu CAI ,  Xiangjing ZHUO ,  Gang YAO ,  Wei CHENG

IPC: H01L33/12 ,  H01L33/06 ,  H01L33/32

CPC classification number: H01L33/12 ,  H01L33/06 ,  H01L33/32

Abstract: The present disclosure provides a semiconductor epitaxial structure, including a substrate, a first-type semiconductor layer, an active region comprising at least one quantum layer, and a second-type semiconductor layer sequentially stacked on a surface of the substrate; wherein the quantum layer comprises barrier layers and potential well layers, and the barrier layers are alternately stacked with the potential well layers, and wherein the quantum layer further comprises a growth temperature transition layer between a barrier layer and a potential well layer, or an electron confinement layer between a barrier layer and a potential well layer.