-
公开(公告)号：US11257710B2
公开(公告)日：2022-02-22
申请号：US16739128
申请日：2020-01-10
发明人： Woo-Song Ahn , Yongchul Oh
IPC分类号： H01L21/308 , H01L21/768 , H01L27/108 , H01L21/311
摘要： A method comprises: disposing an ashing resistive layer over a multi-layered mask; sequentially disposing a first and second dummy layer on the ashing resistive layer; sequentially forming a first pattern structure and a second pattern structure there-over over the second dummy layer; recessing the second dummy layer, through the first and the second pattern structure, to partially expose the first dummy layer and to form a target pattern structure defining a target pattern; performing an anisotropic etching process, through the target pattern structure, to recess the exposed portions of the first dummy layer such that the target pattern is transferred to the recessed first dummy layer; performing an ashing process to remove the target pattern structure; and performing a pattern transferring process by recessing the ashing resistive layer and the multi-layered mask through the recessed first dummy layer to transfer the target pattern to the multi-layered mask.
-
公开(公告)号：US11245019B2
公开(公告)日：2022-02-08
申请号：US16739129
申请日：2020-01-10
发明人： Woo-Song Ahn , Sang-Don Yi , Yongchul Oh
IPC分类号： H01L29/423 , H01L29/51 , H01L29/66 , H01L27/108 , H01L49/02
摘要： A semiconductor device includes a substrate, a gate feature, a gate spacer, and a dielectric layer. The gate feature is above the substrate and includes a gate electrode. The gate spacer is on a sidewall of the gate feature. The dielectric layer is in contact with the gate spacer and has a larger thickness than the gate electrode.
-
搜索结果
2 条记录 (耗时 0.015 秒)
