公开(公告)号：US20190305007A1

公开(公告)日：2019-10-03

申请号：US16170050

申请日：2018-10-25

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Chuan WANG

IPC: H01L27/12

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof and a display. By forming a source pattern layer on the base substrate in the present disclosure, the source pattern layer crossing the gate pattern layer maybe mutually insulated from the gate pattern layer through the insulating buffer layer, thus eliminating the dielectric layer in the prior art which is formed to insulate the source pattern layer and the gate pattern layer, further simplifying the structure of the array substrate, and reducing the process steps and process costs.

公开(公告)号：US20200174325A1

公开(公告)日：2020-06-04

申请号：US16630507

申请日：2018-11-29

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Chuan WANG

IPC: G02F1/1362 ,  H01L23/60 ,  H01L27/12 ,  H01L27/02

Abstract: An array substrate and a display device are provided. An antistatic conductive wire is disposed in the non-display region, and the antistatic conductive wire comprises at least two antistatic conductive layers. An antistatic conductive layer is firstly formed in the fabrication processes, and the antistatic conductive layer has a function of antistatic to prevent static electricity from generating in the processes. After other antistatic conductive layers are formed, a capacitor structure is formed between antistatic conductive layers. Meanwhile, the static discharge is more easily performed in the opposite direction of the antistatic conductive multi-layer.

公开(公告)号：US20190267405A1

公开(公告)日：2019-08-29

申请号：US16044974

申请日：2018-07-25

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Chuan WANG ,  Meng ZHOU ,  Xiaojiang YU

IPC: H01L27/12 ,  G06F3/041 ,  H01L23/538

Abstract: An array substrate provided comprises a gate insulating layer, touch control element and first conducting wire disposed on a substrate; insulating interlayer covering gate insulating layer, touch control element and first conducting wire; protective wire arranged along the surface periphery of insulating interlayer; planarization layer covering insulating interlayer and protective wire, and second conducting wire disposed on surface of planarization layer; wherein touch control element is insulated from first conducting wire comprising an extension section, and free end of extension section is a first end; protective wire is electrically connected with first end; second conducting wire comprises a second and third end arranged oppositely and a contact position between second and third end; second end is electrically connected with touch control element, and contact position is electrically connected with a portion of first conducting wire inner substrate. A display panel and manufacturing method thereof are further provided.

公开(公告)号：US20210072577A1

公开(公告)日：2021-03-11

申请号：US16349663

申请日：2018-11-14

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Chuan WANG

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  H01L27/12 ,  H01L29/423 ,  H01L23/552

Abstract: The present invention discloses a thin film transistor array substrate, a manufacturing method thereof, and a display panel. In the present invention, a width of the channel is increased by cooperation of an electrically connection between the interdigital gate and the interdigital light-shielding layer with design of the interdigital gate. When a width/length ratio (W/L) of the channels in a single thin film crystal device is maintained constant, an increase in the channel width allows the width of the channel layer occupied by the channels to be reduced while maintaining the total width of the channels in the single thin film transistor constant, thereby reducing the area occupied by the single thin film transistor device.

公开(公告)号：US20210286217A1

公开(公告)日：2021-09-16

申请号：US16626547

申请日：2019-03-19

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Chuan WANG

IPC: G02F1/1343

Abstract: An array substrate is provided. The array substrate includes: a plurality of pixel units arranged in an array. Each pixel unit correspondingly includes: a first electrode layer disposed on a glass substrate; a dielectric layer disposed on a surface of the first electrode layer; and a second electrode layer disposed on a surface of the dielectric layer. The second electrode layer includes a patterned electrode pattern. The electrode pattern includes a main electrode pattern and at least one auxiliary electrode pattern correspondingly on at least one side of the main electrode pattern, the at least one auxiliary electrode pattern is electrically connected to the first electrode layer correspondingly through at least one via.