公开(公告)号：US11586497B1

公开(公告)日：2023-02-21

申请号：US17023513

申请日：2020-09-17

申请人： United States of America as represented by the Administrator of NASA

发明人： Alessandro Geist ,  Cody Brewer ,  Robin A. Ripley ,  Christopher M. Wilson ,  Nicholas Franconi ,  Gary A. Crum ,  David J. Petrick ,  Thomas P. Flatley

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F30/34 ,  H03M13/19 ,  G06F11/16

摘要： The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.

公开(公告)号：US12118234B1

公开(公告)日：2024-10-15

申请号：US17893427

申请日：2022-08-23

申请人： United States of America as represented by the Administrator of NASA

发明人： Alessandro Geist ,  Christopher Wilson ,  Cody Brewer ,  Austin Lanham ,  Nicholas Franconi ,  Travis Wise

IPC分类号： G06F12/00 ,  G06F3/06

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

摘要： The present invention relates to a single-board solid state data recorder (SSDR) card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, which includes: a field programmable gate array (FPGA): a plurality of NAND storage banks of non-volatile NAND Flash storage, the plurality of NAND storage banks which store operational data, each of which is controlled by a NAND Flash controller which controls the signaling of the plurality of NAND storage banks and reading and writing to the plurality of NAND storage banks; and a plurality of SpaceWire nodes and a plurality of multi-gigabit transceivers which command the SSDR card and read/write data to the SSDR card; wherein the plurality of NAND Flash memory banks is independently controlled and independently powered.