公开(公告)号：US06661334B1

公开(公告)日：2003-12-09

申请号：US09678601

申请日：2000-09-26

申请人： Thomas W Ives ,  Robert A. Rust ,  Barry J Oldfield

发明人： Thomas W Ives ,  Robert A. Rust ,  Barry J Oldfield

IPC分类号： G05B1900

CPC分类号： G05B19/128 ,  G05B19/048 ,  G05B2219/21076 ,  G11B33/124

摘要： A verification system for an interchangeable component configured to be mated with a receiving system. The system includes a key device supported by the interchangeable component. The key device includes a transmitter configured to transmit a signal comprising component identification characteristics. The system further includes a lock system having a signal receiver and a verification component. The signal receiver is configured to receive the signal from the key device transmitter and pass the signal to the verification component. The verification component is configured to use the signal to determine whether or not the component should be admitted to the receiving system, and to generate an authorization signal if the component should be admitted.

摘要翻译： 用于可配置成与接收系统配合的可互换组件的验证系统。 该系统包括由可互换组件支持的关键设备。 关键装置包括被配置为发射包括部件识别特性的信号的发射机。 该系统还包括具有信号接收器和验证部件的锁定系统。 信号接收器被配置为从密钥设备发射机接收信号，并将信号传递给验证部件。 验证组件被配置为使用该信号来确定组件是否应该被允许进入接收系统，并且如果组件应该被允许，则生成授权信号。

公开(公告)号：US07020803B2

公开(公告)日：2006-03-28

申请号：US10097054

申请日：2002-03-11

申请人： Dale Haddon Wolin ,  Barry J Oldfield ,  Robert A. Rust

发明人： Dale Haddon Wolin ,  Barry J Oldfield ,  Robert A. Rust

IPC分类号： G06F11/00

CPC分类号： G06F11/2215

摘要： The system and methods described herein relate to testing and verifying the fault tolerance in fault tolerant systems. Fault logic integrated into a fault tolerant system permits automated testing of fault paths in system firmware and hardware dedicated to handling fault scenarios. Advantages of the disclosed system and methods include the ability to inject errors without the need to modify system firmware or hardware. Errors can be injected in a controlled manner and asynchronously to normal system firmware execution which permits improved coverage of firmware error paths. The automated error injection capability disclosed is applicable in both the development and production of fault tolerant systems.

公开(公告)号：US06622285B1

公开(公告)日：2003-09-16

申请号：US09706315

申请日：2000-11-02

申请人： Robert A. Rust ,  Barry J Oldfield

发明人： Robert A. Rust ,  Barry J Oldfield

IPC分类号： G06F1100

CPC分类号： G06F11/0727 ,  G06F11/079

摘要： Methods and systems for fault location are described. In one described embodiment, an “in circuit” solution is provided for locating faults along a passive transmission line. Once a fault occurs, various hardware gathers information that is necessary to determine which of a number of different replaceable components has failed. This enables the subsystem to properly respond to the fault condition and thereby eliminate any guessing that could potentially lead to loss of data availability. In the particular described embodiment, signals are driven and received through a selected input/output (I/O) pad. Logic circuitry is provided and launches a wave onto the passive transmission line. Immediately following the launching of the wave, the I/O pad is monitored and can sense the reflections from the wave that has just been launched. By analyzing the reflections, and more specifically the time that it takes for the reflection to be sensed, a determination is made as to the fault location. Once the fault location (or distance thereto) is ascertained, a determination can be made as to which component has failed. At this point, an intelligent decision can be made as to which component should continue operation.

摘要翻译： 描述故障定位的方法和系统。 在一个描述的实施例中，提供了一种“在线”解决方案，用于沿着被动传输线定位故障。 一旦发生故障，各种硬件收集必要的信息，以确定多个不同的可替换组件中的哪一个已经失败。 这使得子系统能够对故障状况进行适当的响应，从而消除可能导致数据可用性损失的任何猜测。 在具体描述的实施例中，通过所选择的输入/输出（I / O）焊盘来驱动和接收信号。 提供逻辑电路，并在无源传输线上发射波。 在发射波浪之后，I / O板被监控，并且可以感测刚刚发射的波形的反射。 通过分析反射，更准确地说，检测反射所需的时间，就确定了故障位置。 一旦确定了故障位置（或其距离），就可以确定哪个部件已经失败。 在这一点上，可以做出关于哪个组件应该继续运行的智能决定。

公开(公告)号：US06687872B2

公开(公告)日：2004-02-03

申请号：US09808910

申请日：2001-03-14

申请人： Barry J Oldfield ,  Robert A. Rust

发明人： Barry J Oldfield ,  Robert A. Rust

IPC分类号： G06F1100

CPC分类号： G06F11/1076 ,  G06F2211/1054 ,  G06F2211/1057

摘要： A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. In one embodiment, parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC). The ASIC includes one or more result buffers for holding intermediate computation results, one or more mathematical operator components configured to receive data segments and coefficients associated with the data segments and operate on them to provide intermediate computation results that can be written to the one or more result buffers, and one or more feedback lines. The feedback lines are coupled between an associated result buffer and an associated mathematical operator component and provide an intermediate computation result to the math operator for use in calculating parity segments.

公开(公告)号：US06567891B2

公开(公告)日：2003-05-20

申请号：US09808648

申请日：2001-03-14

申请人： Barry J Oldfield ,  Robert A. Rust

发明人： Barry J Oldfield ,  Robert A. Rust

IPC分类号： G06F1200

CPC分类号： G06F11/1076

摘要： A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. Parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC). The ASIC includes one or more local result buffers for holding intermediate computation results, one or more mathematical operator components configured to receive data strips, which are portions of larger data stripes, coefficients associated with the data strips, and operates on them to provide intermediate computation results that can be written to the local result buffers Upon completing the parity processing of a strip, the results are then stored in an external memory (e.g., RAM). Upon completing the processing of all of the strips in a stripe, the final parity results are written to applicable sections of a stripe-based disk array.

摘要翻译： 磁盘控制器包括可由微处理器和硬件奇偶校验逻辑访问的存储器。 奇偶校验相关操作由场景识别，并且奇偶校验系数子集存储在每个不同奇偶校验相关计算场景的存储表中。 为了执行特定的奇偶校验相关操作，微处理器确定操作的场景并识别相应的系数子集。 然后使用所识别的系数子集来指示硬件奇偶校验逻辑执行适当的奇偶校验计算。 奇偶校验段由体现为专用集成电路（ASIC）的奇偶校验段计算模块计算。 ASIC包括用于保持中间计算结果的一个或多个本地结果缓冲器，一个或多个数学运算器组件，被配置为接收数据带，其是较大数据条带的部分，与数据条相关联的系数，并且对它们进行操作以提供中间计算 可以写入本地结果缓冲区的结果完成条带的奇偶校验处理后，将结果存储在外部存储器（例如RAM）中。 在完成条纹中所有条带的处理后，最终的奇偶校验结果将写入基于条带的磁盘阵列的可应用部分。

公开(公告)号：US06870466B2

公开(公告)日：2005-03-22

申请号：US10116183

申请日：2002-04-03

申请人： Robert A. Rust ,  Barry J Oldfield

发明人： Robert A. Rust ,  Barry J Oldfield

IPC分类号： A63B33/00 ,  A63B71/06 ,  G08B23/00

CPC分类号： A63B24/0021 ,  A63B33/002 ,  A63B71/0605 ,  A63B2024/0025 ,  A63B2071/0666 ,  A63B2220/836 ,  A63B2225/50 ,  G09B19/0038

摘要： A method and apparatus for monitoring the movement of an object traversing a circuit and outputting data with respect thereto. Lap events are recorded and used to calculate a total lap count, split time, and elapsed time for an event that includes the repetitive traversing of a circuit. Physiologic data is monitored in the case where the object is a person. A transponder or transmitter is affixed to a user and a signal having limited range is coupled to a communications and display device when the user comes into range of the device. Each such coupling is accumulated as lap event data. Calculations are made to display the lap count and timing information as well as physiologic data. In one embodiment, the device is implemented in a watertight housing and placed at the bottom of a swimming pool. The displayed information is visible to a swimmer wearing the transponder or transmitter. In another embodiment, the display is incorporated into eyewear worn by the person traversing a repetitive circuit.

摘要翻译： 一种用于监视穿过电路的物体的移动并相对于其输出数据的方法和装置。 记录笔记事件并用于计算包括电路重复运行的事件的总笔划数，分割时间和经过时间。 在对象是个人的情况下监视生理数据。 当用户进入设备的范围时，应答器或发射器被附加到用户，并且具有有限范围的信号耦合到通信和显示设备。 每个这样的耦合作为共享事件数据被累积。 进行计算以显示膝盖计数和计时信息以及生理数据。 在一个实施例中，该装置被实施在防水外壳中并且放置在游泳池的底部。 显示的信息对于戴着应答器或发射器的游泳者是可见的。 在另一个实施例中，显示器被并入被穿过重复电路的人佩戴的眼镜中。

公开(公告)号：US06799254B2

公开(公告)日：2004-09-28

申请号：US09808711

申请日：2001-03-14

申请人： Barry J Oldfield ,  Robert A. Rust

发明人： Barry J Oldfield ,  Robert A. Rust

IPC分类号： G06F1200

CPC分类号： G06F13/1626 ,  G06F13/1642

摘要： The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

公开(公告)号：US06766480B2

公开(公告)日：2004-07-20

申请号：US09808713

申请日：2001-03-14

申请人： Barry J Oldfield ,  Robert A. Rust

发明人： Barry J Oldfield ,  Robert A. Rust

IPC分类号： G06F1100

CPC分类号： G06F11/1076 ,  G06F3/0613 ,  G06F3/065 ,  G06F3/0689

摘要： A disk controller includes memory that is accessible by both a microprocessor and an operation logic. Information needed by the operation logic to perform an operation is stored in a task description block in memory by the microprocessor, and a pointer to the task description block is added to a task description block queue. The operation logic is then able to access task description blocks, based on the pointers in the queue, at will and perform the corresponding operations.

摘要翻译： 磁盘控制器包括可由微处理器和操作逻辑访问的存储器。 由操作逻辑执行操作所需的信息由微处理器存储在存储器中的任务描述块中，并且指向任务描述块的指针被添加到任务描述块队列中。 然后，操作逻辑能够根据队列中的指针随意访问任务描述块，并执行相应的操作。

公开(公告)号：US06546459B2

公开(公告)日：2003-04-08

申请号：US09809972

申请日：2001-03-15

申请人： Robert A. Rust ,  Barry J Oldfield ,  Christopher W Johansson ,  Christine Grund

发明人： Robert A. Rust ,  Barry J Oldfield ,  Christopher W Johansson ,  Christine Grund

IPC分类号： G06F1200

CPC分类号： G06F11/2064 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0689 ,  G06F11/2087

摘要： Redundant data storage systems and methods of operating a redundant data storage system are presented. In one aspect of the invention, a redundant data storage system includes: a plurality of storage devices configured to redundantly store digital data; a plurality of transaction originating devices configured to originate a plurality of transactions to control operations of the storage devices; a plurality of parallel data buses configured to communicate data relative to the respective transaction originating devices; and a plurality of transaction processing devices coupled with the parallel data buses and configured to process the transactions in an order according to a transaction ordering protocol common to at least some of the transaction processing devices.