公开(公告)号：US11798979B2

公开(公告)日：2023-10-24

申请号：US17156793

申请日：2021-01-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Elizabeth Costner Stewart ,  Jeffrey A. West ,  Thomas D. Bonifield ,  Joseph Andre Gallegos ,  Jay Sung Chun ,  Zhiyi Yu

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L28/40 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02216 ,  H01L21/02263 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76837 ,  H01L21/7682 ,  H01L21/76825

Abstract: An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.

公开(公告)号：US11087451B2

公开(公告)日：2021-08-10

申请号：US15847600

申请日：2017-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Elizabeth C. Stewart ,  Young Sawk Oh ,  Zhiyi Yu ,  Jeffrey A. West ,  Thomas D. Bonifield

IPC: G06K9/00 ,  G06T7/00

Abstract: A method comprises obtaining a wafer comprising a plurality of components, wherein each of the plurality of components exposes a first surface of the component present in a first focal plane and a second surface of the component present in a second focal plane. The method comprises generating, by an optical tool, a first image of the first surface and a second image of the second surface of one of the plurality of components. The method comprises comparing, by a processor, the first image with a first reference image to produce a first value and the second image with a second reference image to produce a second value. The method comprises generating, by the processor, a wafer map indicating a quality state of the one of the plurality of components based on the first and second values.

公开(公告)号：US10978548B2

公开(公告)日：2021-04-13

申请号：US15348580

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Jeffrey A. West ,  Thomas D. Bonifield ,  Joseph Andre Gallegos ,  Jay Sung Chun ,  Zhiyi Yu

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/311

Abstract: A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.