公开(公告)号：US20230412431A1

公开(公告)日：2023-12-21

申请号：US18241544

申请日：2023-09-01

Applicant: Texas Instruments Incorporated

Inventor： Sadia Arefin KHAN ,  Anant Shankar KAMATH ,  Martin STAEBLER ,  Vikas Kumar THAWANI

IPC: H04L25/02 ,  H02K11/33 ,  H03K19/0175 ,  H03K19/003 ,  H02P27/08

CPC classification number: H04L25/0266 ,  H02K11/33 ,  H03K19/017545 ,  H03K19/00323 ,  H03K19/017509 ,  H02P27/08

Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.

公开(公告)号：US20220021562A1

公开(公告)日：2022-01-20

申请号：US17352663

申请日：2021-06-21

Applicant: Texas Instruments Incorporated

Inventor： Sadia Arefin KHAN ,  Anant Shankar KAMATH ,  Martin STAEBLER ,  Vikas Kumar THAWANI

IPC: H04L25/02 ,  H02K11/33 ,  H02P27/08 ,  H03K19/003 ,  H03K19/0175

Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.