公开(公告)号：US11056966B2

公开(公告)日：2021-07-06

申请号：US16996259

申请日：2020-08-18

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Eduardas Jodka ,  Julian Becker ,  Carsten Stoerk

IPC分类号： H03K99/00 ,  H02M1/08 ,  H03K17/687 ,  H02M3/155 ,  H02M1/00

摘要： A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

公开(公告)号：US20200251976A1

公开(公告)日：2020-08-06

申请号：US16265478

申请日：2019-02-01

申请人： Texas Instruments Incorporated

发明人： Eduardas Jodka ,  Julian Becker ,  Carsten Stoerk

IPC分类号： H02M1/08 ,  H02M3/155 ,  H03K17/687

摘要： A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

公开(公告)号：US10784764B2

公开(公告)日：2020-09-22

申请号：US16265478

申请日：2019-02-01

申请人： Texas Instruments Incorporated

发明人： Eduardas Jodka ,  Julian Becker ,  Carsten Stoerk

IPC分类号： H03K99/00 ,  H02M1/08 ,  H02M3/155 ,  H03K17/687 ,  H02M1/00

摘要： A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

公开(公告)号：US20200381990A1

公开(公告)日：2020-12-03

申请号：US16996259

申请日：2020-08-18

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Eduardas Jodka ,  Julian Becker ,  Carsten Stoerk

IPC分类号： H02M1/08 ,  H02M3/155 ,  H03K17/687

摘要： A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.