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1.发明授权Communication system using PCI-Express and communication method for plurality of nodes connected through a PCI-Express 有权使用PCI-Express的通信系统和通过PCI-Express连接的多个节点的通信方法公开(公告)号：US07484033B2
公开(公告)日：2009-01-27
申请号：US11359580
申请日：2006-02-23
申请人： Hiroshi Ishizawa , Terumasa Haneda , Yuichi Ogawa
发明人： Hiroshi Ishizawa , Terumasa Haneda , Yuichi Ogawa
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： To be able to transmit a response packet to a target, which is the original request source node, even if, after issuing a request from a node to another, a bus ID/a device ID is replaced in the PCI-Express switch before said another node makes a response to the request source node in a PCI-Express communication system, which uses a PCI-Express switch. For that purpose, a unique node ID for indicating each node is set to the nodes, a channel ID is set to each channel used for data transfer, and the node ID of the transfer destination module, the channel ID of a channel used for the data transfer, and the packet type indicating that the packet is a request or a response are set in an address field of a packet of data transfer. For the data transfer, only a memory write request packet routed by address routing is used.
摘要翻译： 为了能够将响应分组发送到作为原始请求源节点的目标，即使在从节点向另一节点发出请求之后，在所述PCI-Express交换机之前，将总线ID /设备ID替换为所述PCI-Express交换机 另一个节点在使用PCI-Express交换机的PCI-Express通信系统中对请求源节点做出响应。 为此，将用于指示每个节点的唯一节点ID设置为节点，将信道ID设置为用于数据传输的每个信道，并且传送目的地模块的节点ID，用于该节点的信道的信道ID 数据传输，以及指示分组是请求或响应的分组类型被设置在数据传送分组的地址字段中。 对于数据传输，仅使用由地址路由路由的存储器写请求分组。
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公开(公告)号：US20070073960A1
公开(公告)日：2007-03-29
申请号：US11604361
申请日：2006-11-27
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： To be able to transmit a response packet to the original request node after a bus ID/a device ID is replaced in the PCI-Express switch for a PCI-Express communication system, a unique node ID for indicating each node is set to the nodes. Additionally, it is confirmed whether or not the packet is transferred in the correct order in a series of packet transfers. For that purpose, a sequence code indicating the sequence number of a packet in a series of packet transfer is set in an address field of a packet of data transfer.
摘要翻译： 为了在PCI-Express通信系统的PCI-Express交换机中替换总线ID /设备ID之后能够将响应分组发送到原始请求节点，用于指示每个节点的唯一节点ID被设置到节点 。 此外，确认在一系列分组传送中分组是否以正确的顺序传送。 为此，在数据传送分组的地址字段中设置表示一系列分组传送中的分组的序列号的序列号。
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公开(公告)号：US20060190772A1
公开(公告)日：2006-08-24
申请号：US11237655
申请日：2005-09-29
IPC分类号： G06F11/00
CPC分类号： H04L1/0082
摘要： A file control system of the present invention is a file control system performing DMA transfer and comprising a plurality of file control devices, each of which is provided between a host computer and an external storage device, a first file control device among the plurality of file control devices, checks the consistency between the data read from a memory and the first error detection code given in advance to the data, changes the error detection code added to the read data from the first error detection code to a second error detection code, when the inconsistency is detected by the check, changes at least a part of the data comprising the second error detection code and the data associated with the second error detection code, and executes DMA-transfer of the data which is changed or is not changed to a second file control device of the transfer destination.
摘要翻译： 本发明的文件控制系统是执行DMA传输的文件控制系统，包括多个文件控制装置，每个文件控制装置设置在主计算机和外部存储装置之间，多个文件中的第一文件控制装置 控制装置检查从存储器读取的数据与预先给出的数据之间的第一错误检测码的一致性，将从第一错误检测码添加到读取数据的错误检测码改变为第二错误检测码，当 通过检查检测到不一致，改变包括第二错误检测码的数据的至少一部分和与第二错误检测码相关联的数据，并且执行被改变或不被改变的数据的DMA传送 传送目的地的第二文件控制装置。
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4.发明申请Direct memory access control method, direct memory access controller, information processing system, and program 有权直接存储器访问控制方法，直接存储器访问控制器，信息处理系统和程序公开(公告)号：US20060168366A1
公开(公告)日：2006-07-27
申请号：US11237666
申请日：2005-09-29
申请人： Terumasa Haneda , Yuichi Ogawa
发明人： Terumasa Haneda , Yuichi Ogawa
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In a DMA control method in which a DMA controller transfers data in memory to an input/output device in accordance with the control information which is provided by a processing device to a DMA controller, a processing device implements a step in which the processing device sets an information block comprising the control information and the data in the memory; a step in which address information of the information block is provided by the processing device to the DMA controller; a step in which the DMA controller reads the information block from the memory based on the address information and extracts the control information; and a step in which the DMA controller transfers the data in the information block to the I/O device based on the control information.
摘要翻译： 在DMA控制方法中，DMA控制器根据由处理装置向DMA控制器提供的控制信息将存储器中的数据传送到输入/输出装置，处理装置执行处理装置设置的步骤 包括所述控制信息和所述存储器中的数据的信息块; 所述处理装置向所述DMA控制器提供所述信息块的地址信息的步骤; DMA控制器基于地址信息从存储器读取信息块并提取控制信息的步骤; 以及DMA控制器基于控制信息将信息块中的数据传送到I / O设备的步骤。
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公开(公告)号：US07552249B2
公开(公告)日：2009-06-23
申请号：US11239069
申请日：2005-09-30
CPC分类号： G06F13/28 , G06F3/0619 , G06F3/0659 , G06F3/0689
摘要： A DMA circuit prevents an erroneous data transfer by a descriptor due to an address failure of memory. When a descriptor is created, the data processing unit writes a pointer, for storing the descriptor, in a predetermined part of the descriptor, and stores the descriptor in memory, and when a DMA engine reads the descriptor from the memory, the DMA engine confirms whether the value is correct, and judges whether a DMA transfer of the data in the memory is possible. For both reading and writing of a descriptor, data corruption due to an address failure can be prevented.
摘要翻译： DMA电路由于存储器的地址故障而阻止由描述符导致的错误数据传输。 当创建描述符时，数据处理单元将用于存储描述符的指针写入描述符的预定部分，并将描述符存储在存储器中，并且当DMA引擎从存储器读取描述符时，DMA引擎确认 该值是否正确，并且判断存储器中的数据是否可以进行DMA传输。 对于描述符的读取和写入，可以防止由于地址失败引起的数据损坏。
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公开(公告)号：US20060218336A1
公开(公告)日：2006-09-28
申请号：US11359580
申请日：2006-02-23
申请人： Hiroshi Ishizawa , Terumasa Haneda , Yuichi Ogawa
发明人： Hiroshi Ishizawa , Terumasa Haneda , Yuichi Ogawa
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： To be able to transmit a response packet to a target, which is the original request source node, even if, after issuing a request from a node to another, a bus ID/a device ID is replaced in the PCI-Express switch before said another node makes a response to the request source node in a PCI-Express communication system, which uses a PCI-Express switch. For that purpose, a unique node ID for indicating each node is set to the nodes, a channel ID is set to each channel used for data transfer, and the node ID of the transfer destination module, the channel ID of a channel used for the data transfer, and the packet type indicating that the packet is a request or a response are set in an address field of a packet of data transfer. For the data transfer, only a memory write request packet routed by address routing is used.
摘要翻译： 为了能够将响应分组发送到作为原始请求源节点的目标，即使在从节点向另一节点发出请求之后，在所述PCI-Express交换机之前，将总线ID /设备ID替换为所述PCI-Express交换机 另一个节点在使用PCI-Express交换机的PCI-Express通信系统中对请求源节点做出响应。 为此，将用于指示每个节点的唯一节点ID设置为节点，将信道ID设置为用于数据传输的每个信道，并且传送目的地模块的节点ID，用于该节点的信道的信道ID 数据传输，以及指示分组是请求或响应的分组类型被设置在数据传送分组的地址字段中。 对于数据传输，仅使用由地址路由路由的存储器写请求分组。
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7.发明申请公开(公告)号：US20050044300A1
公开(公告)日：2005-02-24
申请号：US10785118
申请日：2004-02-25
申请人： Osamu Kimura , Yuichi Ogawa , Terumasa Haneda , Akihito Kobayashi , Koji Uchida , Kazuma Takatsu , Katsuhiko Nagashima
发明人： Osamu Kimura , Yuichi Ogawa , Terumasa Haneda , Akihito Kobayashi , Koji Uchida , Kazuma Takatsu , Katsuhiko Nagashima
CPC分类号： G06F12/0868 , G06F11/2087 , G06F2212/286 , G06F2212/312
摘要： The present invention has been developed to carry out the dual-writing of data in cache memories at a higher speed through a single address designation for the improvement of processing performance. In the present invention, a host interface module produces addressing information for designating two written-in destinations, and a bridge module produces two transferred-to addresses and written-in addresses of the cache memories on the basis of the addressing information so that data to be written is transferred to two management modules corresponding to the two transferred-to addresses to be written at the written-in addresses of the cache memories of the management modules.
摘要翻译： 本发明已被开发为通过单个地址指定以更高的速度对高速缓冲存储器中的数据进行双重写入，以提高处理性能。 在本发明中，主机接口模块产生用于指定两个写入目的地的寻址信息，并且桥接模块基于寻址信息产生高速缓冲存储器的两个转移地址和写入地址，从而将数据 被写入被传送到两个管理模块，该管理模块对应于要写入管理模块的高速缓冲存储器的写入地址的两个传送地址。
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公开(公告)号：US07774513B2
公开(公告)日：2010-08-10
申请号：US11220617
申请日：2005-09-08
申请人： Terumasa Haneda , Yuichi Ogawa , Toshiyuki Yoshida , Yuji Hanaoka
发明人： Terumasa Haneda , Yuichi Ogawa , Toshiyuki Yoshida , Yuji Hanaoka
IPC分类号： G06F13/28 , G06F15/167
CPC分类号： G06F13/28
摘要： A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.
摘要翻译： DMA电路并行操作多个DMA通道，能够减少电路规模和减少开发过程。 频道管理电路依次读取来自控制存储器的每个DMA通道的控制信息，执行分析，并根据划分的DMA控制序列执行状态处理（DMA控制）。 此外，信道管理电路更新控制信息，将控制信息写回控制存储器，并执行多个DMA信道的时分控制。 因此，可以减小电路规模，有助于降低成本，并且可以减少开发过程的数量。
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公开(公告)号：US07765357B2
公开(公告)日：2010-07-27
申请号：US11604361
申请日：2006-11-27
IPC分类号： G06F13/00 , G06F13/36 , G06F15/173
CPC分类号： G06F13/4022
摘要： To be able to transmit a response packet to the original request node after a bus ID/a device ID is replaced in the PCI-Express switch for a PCI-Express communication system, a unique node ID for indicating each node is set to the nodes. Additionally, it is confirmed whether or not the packet is transferred in the correct order in a series of packet transfers. For that purpose, a sequence code indicating the sequence number of a packet in a series of packet transfer is set in an address field of a packet of data transfer.
摘要翻译： 为了在PCI-Express通信系统的PCI-Express交换机中替换总线ID /设备ID之后能够将响应分组发送到原始请求节点，用于指示每个节点的唯一节点ID被设置到节点 。 此外，确认在一系列分组传送中分组是否以正确的顺序传送。 为此，在数据传送分组的地址字段中设置表示一系列分组传送中的分组的序列号的序列号。
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10.发明申请公开(公告)号：US20080104341A1
公开(公告)日：2008-05-01
申请号：US11905373
申请日：2007-09-28
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： In response to a request from a central processing unit (CPU) 11 (i.e., firmware) of a node 10, a transfer control unit 14a of a direct memory access (DMA) controller 14 transmits a message and data to another discretionary node 3 by way of a serial bus 1, a switch 2 or the like. In this event, the firmware stores data to be transmitted, a message, and a descriptor thereof in memory 12. In the case of requesting the transmission of the message, the descriptor contains a flag indicating “whether or not there is a need to wait for a response from the data transmission destination”. If the flag is set to ON, the transfer control unit 14a notifies the firmware of a simulated completion immediately instead of waiting for a completion response from the transmission destination node 3.
摘要翻译： 响应于来自节点10的中央处理单元（CPU）11（即固件）的请求，直接存储器访问（DMA）控制器14的传送控制单元14a将消息和数据发送到另一个可选节点3 通过串行总线1，开关2等。 在这种情况下，固件将要发送的数据，消息及其描述符存储在存储器12中。 在请求发送消息的情况下，描述符包含指示“是否需要等待来自数据发送目的地的响应”的标志。 如果标志设置为ON，则传送控制单元14a立即通知固件仿真完成，而不是等待来自发送目的地节点3的完成响应。
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