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公开(公告)号：US11652673B2
公开(公告)日：2023-05-16
申请号：US17677213
申请日：2022-02-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang , Wen-Hung Huang
CPC classification number: H04L25/03057 , H04L25/0212
Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
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公开(公告)号：US20190088644A1
公开(公告)日：2019-03-21
申请号：US16195104
申请日：2018-11-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang
IPC: H01L27/06
Abstract: A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 μm. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.
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公开(公告)号：US10164758B2
公开(公告)日：2018-12-25
申请号：US15386342
申请日：2016-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang , Mu-Shan Lin , Wen-Hung Huang
Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain.
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Patent Agency Ranking
公开(公告)号：US12034572B2
公开(公告)日：2024-07-09
申请号：US18133976
申请日：2023-04-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang , Wen-Hung Huang
CPC classification number: H04L25/03057 , H04L25/0212
Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
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公开(公告)号：US11521966B2
公开(公告)日：2022-12-06
申请号：US17135750
申请日：2020-12-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang
IPC: H01L27/02 , H01L27/06 , H01L23/522
Abstract: A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 μm. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.
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公开(公告)号：US11271783B2
公开(公告)日：2022-03-08
申请号：US17116792
申请日：2020-12-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang , Wen-Hung Huang
Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
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公开(公告)号：US10134729B2
公开(公告)日：2018-11-20
申请号：US14038800
申请日：2013-09-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang
Abstract: A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 μm. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.
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公开(公告)号：US20150091130A1
公开(公告)日：2015-04-02
申请号：US14038800
申请日：2013-09-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang
IPC: H01L27/02
CPC classification number: H01L27/0688
Abstract: A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 μm. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.
Abstract translation: 堆叠的三维半导体器件包括彼此堆叠并在基底衬底上的多个薄衬底。 薄衬底可以包括约0.1μm的厚度。 在一些实施例中，噪声抑制层被垂直插入在有源设备层之间。 在一些实施例中，每个层包括有源器件部分和噪声抑制部分，并且这些层被布置成使得噪声抑制部分垂直插入有源器件部分之间。 噪声抑制部分包括电力/地面网格中的去耦电容器并且减轻垂直噪声。
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