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公开(公告)号：US20240036876A1
公开(公告)日：2024-02-01
申请号：US18487186
申请日：2023-10-16
发明人： Timothy D. ANDERSON , Duc BUI , Joseph ZBICIAK , Reid E. TATGE
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3838
摘要： Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.
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公开(公告)号：US20220188121A1
公开(公告)日：2022-06-16
申请号：US17688260
申请日：2022-03-07
发明人： Timothy D. ANDERSON , Duc BUI , Joseph ZBICIAK , Reid E. TATGE
IPC分类号： G06F9/38
摘要： Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.
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3.发明申请公开(公告)号：US20200210198A1
公开(公告)日：2020-07-02
申请号：US16685747
申请日：2019-11-15
发明人： Timothy D. ANDERSON , Duc BUI , Joseph ZBICIAK , Reid E. TATGE
摘要： Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor, the method comprising detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.
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