公开(公告)号：US20250062678A1

公开(公告)日：2025-02-20

申请号：US18425138

申请日：2024-01-29

Applicant: Texas Instruments Incorporated

Inventor： Ramakrishnan Venkatraman ,  Vikram Gakhar ,  Nischal R ,  Amrutheshwara Rao KV ,  Madhura Nasare ,  Naman Bafna

IPC: H02M1/088 ,  H02M3/158

Abstract: Described embodiments include a control circuit with a first comparator having a first comparator input receiving a first threshold voltage, and a second comparator input coupled to an output voltage terminal. A second comparator has a third comparator input receiving a second threshold voltage, and a fourth comparator input coupled to a current output terminal. A first logic circuit provides a true signal at its output responsive to a particular number of its inputs receiving a true input. A second logic circuit has inputs coupled to the first comparator output, and to the first logic output. A variable resistance circuit has an output coupled to a mode detection output. An amplifier has inputs coupled to the variable resistance circuit output, and a third reference voltage source. A duty cycle generation circuit provides a respective pulse width modulation (PWM) signal at each of its respective duty cycle outputs.

公开(公告)号：US20230367938A1

公开(公告)日：2023-11-16

申请号：US18315076

申请日：2023-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Gandhi ,  Ramakrishnan Venkatraman ,  Lakshmanan Balasubramanian ,  Harsh Kumar Sharma

IPC: G06F30/333 ,  G06F30/3308

CPC classification number: G06F30/333 ,  G06F30/3308

Abstract: A method comprises creating an electronic module design having a plurality of electronic components comprising a plurality of low power enabled components and defining a model of functional behavior and of power behavior. The method also comprises identifying sequential element information correlated with an electronic component based on the models of functional and power behavior. the sequential element information comprising a first control signal and a second control signal. A coverage test is generated based on the sequential element information and is configured to quantify behavior of the electronic component based on a relationship of a plurality of activation states of a first control signal to a plurality of activation states of a second control signal. A simulation file is run to simulate operation of the electronic module design, and a performance status of the electronic module design is determined in response to running the simulation file.