专利检索 ap:("Synopsys, Inc.") AND inv:"Martin Ranke" 第 1 页

1.

发明申请
Method to Perform Full Accuracy Hierarchical Block Level Timing Analysis with Parameterized Chip Level Contexts 有权

公开(公告)号：US20180210986A1

公开(公告)日：2018-07-26

申请号：US15414618

申请日：2017-01-24

申请人： Synopsys, Inc.

发明人： Qiuyang Wu , Martin Ranke , Min Li

IPC分类号： G06F17/50

摘要： A method and apparatus for on chip variation path-based pessimism reduction and improving analysis of a hierarchical integrated circuit design in an electrical circuit. The circuit has one or more block circuit levels and a top circuit level. The method in one embodiment comprises characterizing the top circuit level to produce a context function, the context function used by the block circuit level for evaluation.

2.

发明授权
Method to perform full accuracy hierarchical block level timing analysis with parameterized chip level contexts 有权

公开(公告)号：US10423742B2

公开(公告)日：2019-09-24

申请号：US15414618

申请日：2017-01-24

申请人： Synopsys, Inc.

发明人： Qiuyang Wu , Martin Ranke , Min Li

IPC分类号： G06F9/455 , G06F17/50

摘要： A method and apparatus for on chip variation path-based pessimism reduction and improving analysis of a hierarchical integrated circuit design in an electrical circuit. The circuit has one or more block circuit levels and a top circuit level. The method in one embodiment comprises characterizing the top circuit level to produce a context function, the context function used by the block circuit level for evaluation.