Phase-Lock in All-Digital Phase-Locked Loops
    3.
    发明申请
    Phase-Lock in All-Digital Phase-Locked Loops 失效
    全数字锁相环锁相

    公开(公告)号:US20110081863A1

    公开(公告)日:2011-04-07

    申请号:US12575196

    申请日:2009-10-07

    申请人: Stefan Mendel

    发明人: Stefan Mendel

    IPC分类号: H03L7/00 H04B7/005

    摘要: This disclosure relates to an all digital phase-lock loop (ADPLL). The ADPLL determines an error generated by a digitally controlled oscillator (DCO) which is operated using a tuning word, stores information related to the error, and compensates for the error based on the stored information.

    摘要翻译: 本公开涉及全数字锁相环(ADPLL)。 ADPLL确定由使用调谐字操作的数控振荡器(DCO)产生的错误,存储与错误有关的信息,并且基于存储的信息来补偿错误。