公开(公告)号：US08027214B2

公开(公告)日：2011-09-27

申请号：US12347867

申请日：2008-12-31

Applicant: Shu-Hsuan Lin ,  Yi-Tzu Chen

Inventor： Shu-Hsuan Lin ,  Yi-Tzu Chen

IPC: G11C7/02

CPC classification number: G11C7/065 ,  G11C11/412

Abstract: Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB) and a second output node. The ICL includes a first pull down FET between the first output node and an enable FET connected to electrical ground, and a second pull down FET between the second output node and the enable FET. Channel widths of the second pull down FET and the second gate FET are greater than channel widths of the first pull down FET and the first gate FET to enhance the ability to detect a one (1) and a zero (0) stored in a memory cell connected to the sense amplifier.

Abstract translation: 用于确定存储器单元的状态的感测电路包括读出放大器。 读出放大器包括不平衡交叉耦合锁存器（ICL），位线（BL）和第一输出节点之间的第一栅极场效应晶体管（FET）和位线反相（BLB）与第 第二个输出节点。 ICL包括在第一输出节点和连接到电接地的使能FET之间的第一下拉FET，以及在第二输出节点和使能FET之间的第二下拉FET。 第二下拉FET和第二栅极FET的沟道宽度大于第一下拉FET和第一栅极FET的沟道宽度，以增强检测存储在存储器中的一（1）和零（0）的能力 单元连接到读出放大器。

公开(公告)号：US20110317506A1

公开(公告)日：2011-12-29

申请号：US13224942

申请日：2011-09-02

Applicant: Shu-Hsuan Lin ,  Yi-Tzu Chen

Inventor： Shu-Hsuan Lin ,  Yi-Tzu Chen

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C11/412

Abstract: Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), the ICL outputting a logic low value if the a difference between the a voltage on the BL and a voltage on the BLB exceeds a threshold. Sensing the voltages includes providing at least a first and a second pull down field effect transistor (FET) each having a channel coupled between the first and second output nodes and a ground node, respectively, in a cross coupled arrangement, wherein the second pull down FET has a channel width that is greater than a channel width of the first pull down FET. Additional methods are disclosed.

Abstract translation: 用于确定存储器单元的状态的方法包括使用非对称读出放大器。 这些方法包括通过将BL耦合到不平衡交叉耦合锁存器（ICL）的第一输出节点来感测位线（BL）和位线条（BLB）信号上的电压，如果a BL上的电压和BLB上的电压之间的差异超过阈值。 感测电压包括提供至少第一和第二下拉场效应晶体管（FET），每个第一和第二下拉场效应晶体管分别以交叉耦合的布置耦合在第一和第二输出节点之间的信道和接地节点，其中第二次下拉 FET具有大于第一下拉FET的沟道宽度的沟道宽度。 公开了另外的方法。

公开(公告)号：US08208331B2

公开(公告)日：2012-06-26

申请号：US13224942

申请日：2011-09-02

Applicant: Shu-Hsuan Lin ,  Yi-Tzu Chen

Inventor： Shu-Hsuan Lin ,  Yi-Tzu Chen

IPC: G11C7/02

CPC classification number: G11C7/065 ,  G11C11/412

Abstract: Methods for determining the state of memory cells include using an asymmetric sense amplifier. The methods include sensing the voltages on bit line (BL) and bit line bar (BLB) signals by coupling the BL to a first output node of an imbalanced cross-coupled latch (ICL), the ICL outputting a logic low value if the a difference between the a voltage on the BL and a voltage on the BLB exceeds a threshold. Sensing the voltages includes providing at least a first and a second pull down field effect transistor (FET) each having a channel coupled between the first and second output nodes and a ground node, respectively, in a cross coupled arrangement, wherein the second pull down FET has a channel width that is greater than a channel width of the first pull down FET. Additional methods are disclosed.

Abstract translation: 用于确定存储器单元的状态的方法包括使用非对称读出放大器。 这些方法包括通过将BL耦合到不平衡交叉耦合锁存器（ICL）的第一输出节点来感测位线（BL）和位线条（BLB）信号上的电压，如果a BL上的电压和BLB上的电压之间的差异超过阈值。 感测电压包括提供至少第一和第二下拉场效应晶体管（FET），每个第一和第二下拉场效应晶体管分别以交叉耦合的布置耦合在第一和第二输出节点之间的信道和接地节点，其中第二次下拉 FET具有大于第一下拉FET的沟道宽度的沟道宽度。 公开了另外的方法。

公开(公告)号：US20100165767A1

公开(公告)日：2010-07-01

申请号：US12347867

申请日：2008-12-31

Applicant: Shu-Hsuan Lin ,  Yi-Tzu Chen

Inventor： Shu-Hsuan Lin ,  Yi-Tzu Chen

IPC: G11C7/00 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C11/412

Abstract: Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate FET between a bit line inverse (BLB) and a second output node. The ICL includes a first pull down FET between the first output node and an enable FET connected to electrical ground, and a second pull down FET between the second output node and the enable FET. Channel widths of the second pull down FET and the second gate FET are greater than channel widths of the first pull down FET and the first gate FET to enhance the ability to detect a one (1) and a zero (0) stored in a memory cell connected to the sense amplifier.

Abstract translation: 用于确定存储器单元的状态的感测电路包括读出放大器。 读出放大器包括不平衡交叉耦合锁存器（ICL），位线（BL）和第一输出节点之间的第一栅极场效应晶体管（FET）和位线反相（BLB）与第 第二个输出节点。 ICL包括在第一输出节点和连接到电接地的使能FET之间的第一下拉FET，以及在第二输出节点和使能FET之间的第二下拉FET。 第二下拉FET和第二栅极FET的沟道宽度大于第一下拉FET和第一栅极FET的沟道宽度，以增强检测存储在存储器中的一（1）和零（0）的能力 单元连接到读出放大器。

公开(公告)号：US07613054B2

公开(公告)日：2009-11-03

申请号：US11924437

申请日：2007-10-25

Applicant: Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

Inventor： Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

Abstract translation: SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线 局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

公开(公告)号：US20090109768A1

公开(公告)日：2009-04-30

申请号：US11924437

申请日：2007-10-25

Applicant: Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

Inventor： Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

Abstract translation: SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线 局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。