公开(公告)号：US12099642B2

公开(公告)日：2024-09-24

申请号：US17712395

申请日：2022-04-04

Applicant: Seagate Technology LLC

Inventor： Rajesh Maruti Bhagwat ,  Hemant Vitthalrao Mane ,  Avinash Suresh Pisal ,  Niranjan Anant Pol

IPC: G06F21/56 ,  G06F21/57 ,  G06F21/71 ,  G06F21/79 ,  G06F21/85

CPC classification number: G06F21/85 ,  G06F21/57

Abstract: A data storage system can have a hardware interposer connected inline between a plurality of controllers and a plurality of memories. A bus of the hardware interposer may be monitored with a security breach monitor of the hardware interposer to allow a deviation from a predetermined address range to be detected by the security breach monitor, which prompts the security breach monitor to block access through the hardware interposer for a first controller of the plurality of controllers.

公开(公告)号：US12061701B2

公开(公告)日：2024-08-13

申请号：US17165675

申请日：2021-02-02

Applicant: Seagate Technology LLC

Inventor： Hemant Mane ,  Rajesh Maruti Bhagwat ,  Avinash Suresh Pisal ,  Niranjan Anant Pol

IPC: G06F21/57 ,  G06F3/06 ,  G06F8/65 ,  G06F9/445 ,  G06F13/10 ,  G06F13/42

CPC classification number: G06F21/572 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F8/65 ,  G06F9/44589 ,  G06F13/105 ,  G06F13/4282 ,  G06F2213/00

Abstract: An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.

公开(公告)号：US20230259661A1

公开(公告)日：2023-08-17

申请号：US17712395

申请日：2022-04-04

Applicant: Seagate Technology LLC

Inventor： Rajesh Maruti Bhagwat ,  Hemant Vitthalrao Mane ,  Avinash Suresh Pisal ,  Niranjan Anant Pol

IPC: G06F21/85 ,  G06F21/57

CPC classification number: G06F21/85 ,  G06F21/57

Abstract: A data storage system can have a hardware interposer connected inline between a plurality of controllers and a plurality of memories. A bus of the hardware interposer may be monitored with a security breach monitor of the hardware interposer to allow a deviation from a predetermined address range to be detected by the security breach monitor, which prompts the security breach monitor to block access through the hardware interposer for a first controller of the plurality of controllers.