公开(公告)号：US20250117656A1

公开(公告)日：2025-04-10

申请号：US18983603

申请日：2024-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Songhwai OH ,  Yunho CHOI ,  Kyungjae LEE

IPC: G06N3/08 ,  G06F17/18 ,  G06N3/04 ,  G06N3/047

Abstract: A neural network device and an action selecting method using the same, which select an action corresponding to a current state on the basis of a value return. A method of selecting, executed by at least one processor, an action on the basis of deep learning includes receiving a current state as an input, calculating a value distribution corresponding to each of a plurality of actions to be performed on the current state, and selecting an optimal action from among the plurality of actions based on the value distribution, wherein the value distribution includes at least one Gaussian graph following a Gaussian distribution.

公开(公告)号：US20250124208A1

公开(公告)日：2025-04-17

申请号：US18913333

申请日：2024-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunho CHOI ,  Junhyeok SONG ,  Junhuck LEE ,  Jaegyeong CHOI

IPC: G06F30/392 ,  G06F115/02

Abstract: A layout design method includes receiving input data defining a semiconductor integrated circuit, performing an arrangement operation and a routing operation based on the input data to obtain a first layout of the semiconductor integrated circuit including plural blocks, setting, on the first layout, a first switch area in which first switches are to be arranged, and arranging the first switches in the first switch area, and arranging second switches in a second switch area that is different from the first switch area to obtain a second layout of the semiconductor integrated circuit.

公开(公告)号：US20210287965A1

公开(公告)日：2021-09-16

申请号：US17104124

申请日：2020-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woonki LEE ,  Daehyung MYUNG ,  Yunho CHOI ,  Minsic KIM ,  Seunghun OH ,  Jinhyeong KIM ,  Junyeong AN ,  Jooyeon LEE ,  Sangwoo PYO

IPC: H01L23/49 ,  H01L23/00 ,  H01L27/02

Abstract: A semiconductor device includes a substrate, input/output areas in a first direction and a second direction, parallel to an upper surface of the substrate and intersecting to each other, the input/output areas each including semiconductor elements providing an input/output circuit, lower wiring patterns connected to the semiconductor elements, and input/output pins connected to the lower wiring patterns, and bumps connected to the input/output pins by upper wiring patterns on the same layer as the input/output pins. The input/output areas include a first input/output area and a second input/output area, and each of the first input/output area and the second input/output area includes a first area and a second area sequentially in the first direction, and in the first input/output area, the input/output pin is in the first area, and in the second input/output area, the input/output pin is in the second area.