公开(公告)号：US20190043813A1

公开(公告)日：2019-02-07

申请号：US16159290

申请日：2018-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-dae KIM ,  Hyung-gil BAEK ,  Yun-rae CHO ,  Nam-gyu BAEK

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/78

Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.

公开(公告)号：US20200035649A1

公开(公告)日：2020-01-30

申请号：US16376440

申请日：2019-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-nee JANG ,  Nam-gyu BAEK ,  Yun-rae CHO ,  Seung-hun HAN

IPC: H01L25/065

Abstract: A semiconductor package includes a package substrate, a plurality of external connections under the package substrate, a master chip on the package substrate, at least one slave chip on the master chip, a plurality of first bumps and a plurality of second bumps between the package substrate and the master chip, and a plurality of wires connecting the package substrate to the at least one slave chip. The package substrate includes a plurality of first paths connecting the plurality of first bumps to the plurality of external connections and a plurality of second paths connecting the plurality of second bumps to the plurality of wires. An upper surface of the package substrate includes a first edge and a second edge that extend in a first direction and a third edge and a fourth edge that extend in a second direction.