公开(公告)号：US20230232627A1

公开(公告)日：2023-07-20

申请号：US17879874

申请日：2022-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Kyu LEE ,  Yu Jin KIM ,  Guk Hyon YON

IPC: H01L27/11582 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor memory device includes a first substrate defining a cell array region, a mold structure including a plurality of gate electrodes sequentially spaced and stacked on the first substrate in a step form, and a channel hole defined as penetrating the plurality of gate electrodes on the cell array region in a vertical direction perpendicular to an upper surface of the first substrate. The device includes an information storage layer along side walls and a bottom surface of the channel hole, the information storage layer including a blocking insulation layer along the side walls and the bottom surface of the channel hole, a charge storage layer on the blocking insulation layer, and a tunneling insulation layer. The device includes a channel layer on the information storage layer inside the channel hole, and an insulation pattern arranged to fill the channel hole on the channel layer.