公开(公告)号：US08952510B2

公开(公告)日：2015-02-10

申请号：US14061784

申请日：2013-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Sang Cho ,  Chang-Sig Kang ,  Dae-Woo Son ,  Yun-Seok Choi ,  Kyong-Soon Cho ,  Sang-Heui Lee

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/50 ,  H01L23/4985 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/0405 ,  H01L2224/05553 ,  H01L2224/06155 ,  H01L2224/14155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14

Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads include first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.

Abstract translation: 用于TAB封装的半导体芯片包括包括连接到芯片的内部电路并用于接收外部信号的一组输入焊盘的表面。该表面包括输出焊盘。 多个输入焊盘与第一边缘相邻并且处于基本上平行于第一边缘并沿第一方向延伸的第一行; 多个第一输出焊盘与第二边缘相邻，并且处于基本上平行于第二边缘并沿第一方向延伸的第二行; 并且多个第二输出焊盘位于第一行和第二行之间。 多个第二输出焊盘包括位于距相应的第三边缘和第四边缘一定距离的第一和第二最外面的焊盘，以及第一和第二内部焊盘位于距相应的第三边缘和第四边缘更大的距离处。

公开(公告)号：US20140084430A1

公开(公告)日：2014-03-27

申请号：US14061784

申请日：2013-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Sang Cho ,  Chang-Sig Kang ,  Dae-Woo Son ,  Yun-Seok Choi ,  Kyong-Soon Cho ,  Sang-Heui Lee

IPC: H01L23/00

CPC classification number: H01L24/50 ,  H01L23/4985 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/0405 ,  H01L2224/05553 ,  H01L2224/06155 ,  H01L2224/14155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14

Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.

Abstract translation: 用于TAB封装的半导体芯片包括包括连接到芯片的内部电路并用于接收外部信号的一组输入焊盘的表面。该表面包括输出焊盘。 多个输入焊盘与第一边缘相邻并且处于基本上平行于第一边缘并沿第一方向延伸的第一行; 多个第一输出焊盘与第二边缘相邻，并且处于基本上平行于第二边缘并沿第一方向延伸的第二行; 并且多个第二输出焊盘位于第一行和第二行之间。 多个第二输出焊盘第一和第二最外面焊盘位于相应的第三边缘和第四边缘一定距离处，并且第一和第二内部焊盘位于距相应的第三边缘和第四边缘更大的距离处。

公开(公告)号：US09356450B2

公开(公告)日：2016-05-31

申请号：US13766242

申请日：2013-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hun Jeon ,  Iksung Park ,  Young-Sang Cho

IPC: H02J7/00 ,  H02J9/06

CPC classification number: H02J7/00 ,  H02J9/061

Abstract: A power supply circuit includes a sequence control circuit configured to generate at least one control signal in response to a main power source, a voltage regulator circuit configured to be coupled to the main power source and to selectively generate at least one power supply voltage for a chipset from the main power source in response to the at least one control signal and a discharge circuit configured to discharge the voltage regulator circuit responsive to the at least one control signal.

Abstract translation: 电源电路包括顺序控制电路，其被配置为响应于主电源而产生至少一个控制信号;电压调节器电路，被配置为耦合到主电源并选择性地产生至少一个电源电压 响应于所述至少一个控制信号从主电源提供芯片组;以及放电电路，其被配置为响应于所述至少一个控制信号对所述稳压器电路进行放电。